1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 1.2
48-Pin TSOP1 Contact x8 Device (2 CE 8 Gb)
NC
NC
NC
NC
NC
R/B2#
R/B1#
RE#
CE1#
CE2#
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1
48
12
13
NAND Flash
TSOP1
(x8)
37
36
24
25
VSS
(1)
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
VCC
(1)
NC
VCC
VSS
NC
VCC
(1)
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
VSS
(1)
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Document Number: 002-00483 Rev. *H
Page 3 of 21
S34ML08G1
Figure 1.3
63-BGA Contact, x8 Device, Single CE (Top View)
A1
NC
B1
NC
A2
NC
A9
NC
B9
NC
C3
WP#
D3
VCC
(1)
E3
NC
F3
NC
G3
NC
H3
NC
J3
NC
K3
V
SS
C4
ALE
D4
RE#
E4
NC
F4
NC
G4
VCC
(1)
H4
I/O0
J4
I/O1
K4
I/O2
C5
VSS
D5
CLE
E5
NC
F5
NC
G5
NC
H5
NC
J5
NC
K5
I/O3
C6
CE#
D6
NC
E6
NC
F6
NC
G6
NC
H6
NC
J6
V
CC
K6
I/O4
C7
WE#
D7
NC
E7
NC
F7
VSS
(1)
G7
NC
H7
NC
J7
I/O5
K7
I/O6
C8
RB#
D8
NC
E8
NC
F8
NC
G8
NC
H8
V
cc
J8
I/O7
K8
V
SS
L9
NC
M9
NC
A10
NC
B10
NC
L1
NC
M1
NC
L2
NC
M2
NC
L10
NC
M10
NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Document Number: 002-00483 Rev. *H
Page 4 of 21
S34ML08G1
2.
Pin Description
Table 2.1
Pin Description
Pin Name
I/O0 - I/O7
CLE
ALE
CE#
WE#
RE#
WP#
R/B#
VCC
VSS
NC
Description
Inputs/Outputs.
The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
Command Latch Enable.
This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
Address Latch Enable.
This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
Chip Enable.
This input controls the selection of the device. When the device is not busy CE# low selects the memory.
Write Enable.
This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
Read Enable.
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid t
REA
after the falling edge of RE# which also increments the internal column address counter by one.
Write Protect.
The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
Ready Busy.
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Supply Voltage.
The V
CC
supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
prevents the insertion of Commands when V
CC
is less than V
LKO
.
Ground.
Not Connected.
Notes:
1. A 0.1 µF capacitor should be connected between the V
CC
Supply Voltage pin and the V
SS
Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever V
CC
is below 1.8V to protect the device from any involuntary program/erase during power transitions.
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