SUPPLEMENT
S71KS512SC0
S71KL256SC0
S71KL512SC0
HyperFlash™ and HyperRAM™
Multi-Chip Package 1.8V/3V
HyperFlash™ and HyperRAM™ Multi-Chip Package 3 V
Distinctive Characteristics
■
HyperFlash™ and HyperRAM™ in Multi-Chip Package (MCP)
❐
1.8V, 512 Mb HyperFlash and 64 Mbit HyperRAM
(S71KS512SC0)
❐
3.0V, 512 Mb HyperFlash and 64 Mbit HyperRAM
(S71KL512SC0)
❐
3.0V, 256 Mb HyperFlash and 64 Mbit HyperRAM
(S71KL256SC0)
❐
FBGA 24-ball, 6
8
1.0 mm package
HyperBus Interface
❐
1.8V I/O, 12 bus signals
• Differential clock (CK/CK#)
❐
3.0V I/O, 11 bus signals
• Single ended clock (CK)
❐
Chip Select (CS#)
❐
8-bit data bus (DQ[7:0])
❐
Read-Write Data Strobe (RWDS)
• Bidirectional Data Strobe/Mask
• Output at the start of all transactions to indicate refresh
latency
• Output during read transactions as Read Data Strobe
• Input during write transactions as Write Data Mask (Hyper-
RAM only)
■
Optional Signals
❐
Reset
❐
INT# output to generate external interrupt
• Busy to Ready Transition
❐
RSTO# Output to generate system level Power-On Reset
(POR)
• User configurable RSTO# Low period
High Performance
❐
Double-Data Rate (DDR)
• Two data transfers per clock
❐
Up to 166-MHz clock rate (333 MB/s) at 1.8V V
CC
❐
Up to 100-MHz clock rate (200 MB/s) at 3.0V V
CC
■
■
Cypress Semiconductor Corporation
Document Number: 002-03902 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 23, 2017
SUPPLEMENT
S71KS512SC0
S71KL256SC0
S71KL512SC0
Contents
General Description ......................................................... 3
HyperBus MCP Family with HyperFlash
and HyperRAM ............................................................ 3
HyperBus MCP 3 V Signal Descriptions ......................... 4
HyperBus MCP Block Diagram ....................................... 5
Physical Interface ............................................................. 6
HyperBus MCP — FBGA 24-Ball,
5x5 Array Footprint ...................................................... 6
Physical Diagram ........................................................ 7
Electrical Specifications .................................................. 8
Absolute Maximum Ratings ......................................... 8
DC Characteristics ...................................................... 8
Ordering Part Numbers .................................................. 11
Valid Combinations - Standard .................................. 11
Valid Combinations — Automotive Grade /
AEC-Q100 ................................................................. 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC® Solutions ...................................................... 14
Cypress Developer Community ................................. 14
Technical Support ..................................................... 14
Document Number: 002-03902 Rev. *D
Page 2 of 14
SUPPLEMENT
S71KS512SC0
S71KL256SC0
S71KL512SC0
General Description
This supplementary datasheet provides MCP device related information for a HyperBus MCP family, incorporating both HyperFlash
and HyperRAM memories. The document describes how the features, operation, and ordering options of the related memories have
been enhanced or changed from the standard memory devices incorporated in the MCP. The information contained in this document
modifies any information on the same topics established by the documents listed in
Table 1
and should be used in conjunction with
those documents. This document may also contain information that was not previously covered by the listed documents. The infor-
mation is intended for hardware system designers and software developers of applications, operating systems, or tools.
Table 1. Affected Documents/Related Documents
Title
HyperBus™ Specification Low Signal Count, High Performance DDR Bus
S26KL512S / S26KS512S / S26KL256S / S26KS256S / S26KL128S / S26KS128S, 512 MBIT
(64 MBYTE), 256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte) 1.8V/3.0V HyperFlash
TM
Family
S27KL0641, S27KS0641, S71KL1281, S71KS1281: HyperRAM™ Self-Refresh DRAM 3.0V/
1.8V 64/128 Mbit (8/16 Mbyte)
Cypress Publication Number
001-99253
001-99198
001-97964
HyperBus MCP Family with HyperFlash and HyperRAM
For systems needing both Flash and self-refresh DRAM, the HyperBus products family includes MCP devices that combine
HyperFlash and HyperRAM in a single package. A HyperBus MCP reduces board space and Printed Circuit Board (PCB) signal routing
congestion while also maintaining or improving signal integrity over separately packaged memory configurations.
The HyperBus MCP family offers 1.8V/3V interface HyperFlash densities of 512 Mb (64 Mbyte) and 256 Mb (32 Mbyte) in
combination with HyperRAM 64 Mb (8 Mbyte).
This supplemental datasheet addresses only the MCP related differences from the HyperBus Specification and the individual
HyperFlash and HyperRAM datasheets. For all other information related to the individual memories in the MCP, refer to the
HyperBus, HyperFlash, and HyperRAM datasheets.
Document Number: 002-03902 Rev. *D
Page 3 of 14
SUPPLEMENT
S71KS512SC0
S71KL256SC0
S71KL512SC0
HyperBus MCP 3 V Signal Descriptions
Figure 1. HyperBus MCP Signal Diagram
RESET#
CS1#
CS2#
CK
CK#
V
CC
V
CC
Q
DQ[7:0]
RWDS
INT#
RSTO#
V
SS
V
SS
Q
Table 2. Signal Descriptions
Symbol
CS1#
Type
Input
Description
Chip Select 1: Chip Select for the HyperFlash memory. HyperBus transactions are initiated
with a High to Low transition. HyperBus transactions are terminated with a Low to High
transition.
Chip Select 2: Chip Select for the HyperRAM memory. HyperBus transactions are initiated
with a High to Low transition. HyperBus transactions are terminated with a Low to High
transition.
Single-ended Clock 3.0V: Command-Address/Data information is input or output with respect
to the edges of the CK.
Note: Single-ended clock is available on 3.0V devices only.
Differential Clock 1.8V: Command-Address/Data information is input or output with respect to
the crossing edges of the CK/CK# pair.
Note: Differential clock is available on 1.8V devices only.
Read-Write Data Strobe: Output data during read transactions are edge aligned with RWDS.
RWDS is an input during write transactions to function as a HyperRAM data mask. At the
beginning of all bus transactions RWDS is an output and indicates whether additional initial
latency count is required.
1 = Additional latency count
0 = No additional latency count
Data Input/Output: Command-Address/Data information is transferred on these DQs during
Read and Write transactions.
INT Output (Optional): When Low, the HyperFlash device is indicating that an internal event
has occurred. This signal is intended to be used as a system level interrupt for the device to
indicate that an on-chip event has occurred. INT# is an open-drain output.
Hardware RESET (Optional): When Low, the HyperFlash memory will self initialize and return
to the idle state.
RWDS and DQ[7:0] is placed into the High-Z state when RESET# is Low. RESET# includes
a weak pull-up, if RESET# is left unconnected it will be pulled up to the High state.
RESET# is not connected to the HyperRAM.
RSTO# Output (Optional): RSTO# is an open-drain output used to indicate when a POR is
occurring within the HyperFlash memory and can be used as a system level reset signal. Upon
completion of the internal POR the RSTO# signal will transition from Low to high impedance
after a user defined timeout period has elapsed. Upon transition to the high impedance state
the external pull-up resistance will pull RSTO# High and the device immediately is placed into
the Idle state.
Core Power
Input/Output Power
Core Ground
Input/Output Ground
CS2#
Input
CK
Input
CK/CK#
Input
RWDS
Output
DQ[7:0]
INT#
Input/Output
Output (open drain)
RESET#
Input
RSTO#
Output (open drain)
V
CC
V
CC
Q
V
SS
V
SS
Q
Power Supply
Power Supply
Power Supply
Power Supply
Document Number: 002-03902 Rev. *D
Page 4 of 14
SUPPLEMENT
S71KS512SC0
S71KL256SC0
S71KL512SC0
HyperBus MCP Block Diagram
Figure 2. HyperBus Connections Including Optional Signals
MCP
Master
V
CC
V
CC
Q
CS0#
CK
CK#
DQ[7:0]
RWDS
CS1#
Slave 0
HyperFlash
CS#
CK
CK#
DQ[7:0]
RWDS
V
CC
V
CC
Q
RESET#
RSTO#
INT#
CS1#
V
SS
V
SS
Q
RESET#
RSTO#
INT#
CS2#
V
SS
V
SS
Q
Slave 1
HyperRAM
CS#
CK
CK#
DQ[7:0]
RWDS
V
CC
V
CC
Q
V
SS
V
SS
Q
Note
1. CK# is for 1.8V devices only.
Document Number: 002-03902 Rev. *D
Page 5 of 14
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