S29WS256N
S29WS128N
256/128 Mbit (16/8 M x 16 bit), 1.8 V,
Simultaneous Read/Write, Burst Flash
This product family has been retired and is not recommended for designs. For new and current designs, the S29WS128P and
S29WS256P supersede the S29WS128N and S29WS256N respectively. These are the factory-recommended migration paths.
Please refer to the S29WS-P Family data sheet for specifications and ordering information.
General Description
The Spansion S29WS256/128 are Mirrorbit
TM
Flash products fabricated on 110 nm process technology. These burst mode Flash
devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using separate
data and address pins. These products can operate up to 80 MHz and use a single V
CC
of 1.7 V to 1.95 V that makes them ideal for
today’s demanding wireless applications requiring higher density, better performance and lowered power consumption.
Distinctive Characteristics
110 nm MirrorBit™ Technology
Dual boot sector configuration (top and bottom)
Offered Packages
WS256N/128N: 84-ball FBGA (8 mm x 11.6 mm)
Low V
CC
write inhibit
Persistent and Password methods of Advanced Sector Protection
Write operation status bits indicate program and erase operation
completion
Suspend and Resume commands for Program and Erase
operations
Simultaneous Read/Write operation with zero latency
32-word Write Buffer
Sixteen-bank architecture consisting of 16/8 Mwords for WS256N/
128N, respectively
Four 16 Kword sectors at both top and bottom of memory array
254/126 64 Kword sectors (WS256N/128N)
Programmable linear (8/16/32) with or without wrap around and
continuous burst read modes
Secured Silicon Sector region consisting of 128 words each for
factory and customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
RDY output indicates data available to system
Command set compatible with JEDEC (42.4) standard
Read Access Times
Speed Option (MHz)
Max. Synch. Latency, ns (t
IACC
)
Max. Synch. Burst Access, ns (t
BACC
)
Max. Asynch. Access Time, ns (t
ACC
)
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Performance Characteristics
80
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Unlock Bypass program command to reduce programming time
Synchronous or Asynchronous program operation, independent of
burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
rN
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66
80
54
80
13.5
80
20
80
13.5
Continuous Burst Read @ 80 MHz
Simultaneous Operation (asynchronous)
Program (asynchronous)
Erase (asynchronous)
Standby Mode (asynchronous)
ew
Current Consumption (typical values)
38 mA
50 mA
19 mA
19 mA
20 µA
R
80
9
11.2
80
20
80
13.5
ot
80
20
80
13.5
Max. Asynch. Page Access Time, ns (t
PACC
)
Max CE# Access Time, ns (t
CE
)
Max OE# Access Time, ns (t
OE
)
N
Single Word Programming
Effective Write Buffer Programming (V
CC
) Per Word
Effective Write Buffer Programming (V
ACC
) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
D
Typical Program & Erase Times
40 µs
9.4 µs
6 µs
150 ms
600 ms
Cypress Semiconductor Corporation
Document Number: 002-01825 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 08, 2016
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Single 1.8 V read/program/erase (1.70–1.95 V)
Hardware (WP#) protection of top and bottom sectors
S29WS256N
S29WS128N
Contents
1.
1.1
2.
3.
4.
4.1
4.2
4.3
5.
6.
6.1
7.
7.1
7.2
7.3
7.4
Ordering Information
................................................... 3
Valid Combinations ........................................................ 3
Input/Output Descriptions & Logic Symbol
.............. 4
Block Diagram..............................................................
5
Physical Dimensions/Connection Diagrams.............
Related Documents .......................................................
Special Handling Instructions for FBGA Package..........
MCP Look-ahead Connection Diagram .........................
5
5
5
7
11.7 DC Characteristics (CMOS Compatible)....................... 54
11.8 AC Characteristics ........................................................ 55
12. Appendix
..................................................................... 72
12.1 Common Flash Memory Interface................................. 75
13.
Document History Page
............................................. 78
Additional Resources
.................................................. 9
9.
9.1
9.2
9.3
9.4
10.
10.1
10.2
10.3
11.
11.1
11.2
11.3
11.4
11.5
11.6
Power Conservation Modes......................................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
Hardware RESET# Input Operation.............................
Output Disable (OE#)...................................................
ot
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Advanced Sector Protection/Unprotection
.............
Lock Register ...............................................................
Persistent Protection Bits.............................................
Dynamic Protection Bits...............................................
Persistent Protection Bit Lock Bit.................................
Password Protection Method .......................................
Advanced Sector Protection Software Examples ........
Hardware Data Protection Methods.............................
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Secured Silicon Sector Flash Memory Region
....... 48
Factory Secured Silicon Sector .................................... 48
Customer Secured Silicon Sector ................................ 49
Secured Silicon Sector Entry/Exit Command
Sequences .................................................................... 49
Electrical Specifications............................................
Absolute Maximum Ratings .........................................
Operating Ranges........................................................
Test Conditions ............................................................
Key to Switching Waveforms .......................................
Switching Waveforms ..................................................
V
CC
Power-up ..............................................................
51
51
52
52
52
53
53
Page 2 of 79
Document Number: 002-01825 Rev. *B
N
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en
Device Operations
.....................................................
Device Operation Table ...............................................
Asynchronous Read.....................................................
Page Read Mode .........................................................
Synchronous (Burst) Read Mode & Configuration
Register........................................................................
7.5 Autoselect ....................................................................
7.6 Program/Erase Operations ..........................................
7.7 Simultaneous Read/Write ............................................
7.8 Writing Commands/Command Sequences..................
7.9 Handshaking ................................................................
7.10 Hardware Reset ...........................................................
7.11 Software Reset ............................................................
14
18
21
38
38
39
39
40
de
41
42
43
44
44
44
46
46
47
47
47
47
47
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12
12
12
13
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Product Overview
...................................................... 10
Memory Map ................................................................ 10
S29WS256N
S29WS128N
1.
Ordering Information
The order number is formed by a valid combinations of the following:
S29WS
256
N
0S
BA
W
01
0
Packing Type
0 = Tray (standard;
(Note 1))
2 = 7-inch Tape and Reel
3 = 13-inch Tape and Reel
Model Number (Note 3)
(DYB Protect/Unprotect After Power-up)
01 = DYB Unprotect
11 = DYB Protect
Temperature Range (Note 3)
W = Wireless (–25°C to +85°C)
Flash Density
256= 256 Mb
128= 128 Mb
1.1
Valid Combinations
ec
S29WS-N Valid Combinations
(1), (2), (3)
om
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
DYB Power
Up State
Unprotect
0, 2, 3
(1)
Protect
Unprotect
Protect
8 mm x 11.6 mm
84-ball
MCP-Compatible
m
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Product Family
S29WS =1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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Packing
Type
Package Type
(2)
Process Technology
N = 110 nm MirrorBit™ Technology
R
Base Ordering
Part Number
S29WS256N
Product
Status
Preliminary
Speed
Option
Package Type, Material,
& Temperature Range
Model
Number
01
0S, 0P, 0L
ot
S29WS128N
Preliminary
0S, 0P, 0L
BAW (Lead (Pb)-free
Compliant),
BFW (Lead (Pb)-free)
N
11
01
11
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading “S29” and packing type designator from ordering part number.
3. For other boot option contact your local sales office.
Document Number: 002-01825 Rev. *B
ew
Speed Option (Burst Frequency)
0S = 80 MHz
0P = 66 MHz
0L = 54 MHz
D
es
Package Type & Material Set
BA = Very Thin Fine-Pitch BGA, Lead (Pb)-free Compliant Package
BF = Very Thin Fine-Pitch BGA, Lead (Pb)-free Package
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Page 3 of 79
S29WS256N
S29WS128N
2.
Input/Output Descriptions & Logic Symbol
Table
identifies the input and output package connections provided on the device.
Input/Output Descriptions
Symbol
A23–A0
DQ15–DQ0
CE#
OE#
WE#
V
CC
V
SS
NC
RDY
CLK
Type
Input
I/O
Input
Input
Input
Supply
I/O
No Connect
Output
Input
Description
Address lines for WS256N (A22-A0 for WS128).
Data input/output.
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
Device Power Supply.
Ground.
Not connected internally.
Ready. Indicates when valid burst data is ready to be read.
AVD#
Input
When high, device ignores address inputs.
RESET#
WP#
ACC
RFU
Input
Input
Input
Reserved
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At V
IL
, disables program and erase functions in the four outermost sectors. Should be at
V
IH
for all other conditions.
Document Number: 002-01825 Rev. *B
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Reserved for future use (see
Figure 4.3,
MCP Look-ahead Diagram
on page 8).
de
Acceleration Input. At V
HH
, accelerates programming; automatically places device in unlock bypass
mode. At V
IL
, disables all program and erase functions. Should be at V
IH
for all other conditions.
d
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Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode, causes
starting address to be latched at the next active clock edge.
D
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter.
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Page 4 of 79
S29WS256N
S29WS128N
3.
Block Diagram
V
CC
V
SS
RDY
Buffer
RDY
Erase Voltage
Generator
WE#
RESET#
WP#
ACC
State
Control
Command
Register
Input/Output
Buffers
DQ15–DQ0
CE#
OE#
ew
D
es
Chip Enable
Output Enable
Logic
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n
PGM Voltage
Generator
Data
Latch
Timer
Address Latch
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fo
V
CC
Detector
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Y-Decoder
Y-Gating
AVD#
CLK
A
max
–A0*
This section shows the I/O designations and package specifications for the S29WS-N.
4.1
Related Documents
The following documents contain information relating to the S29WS-N devices. Click on the title or go to www.amd.com/flash (click
on Technical Documentation) or www.fujitsu.com to download the PDF file, or request a copy from your sales office.
Migration to the S29WS256N Family Application Note
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2
Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data
integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time.
Document Number: 002-01825 Rev. *B
N
4. Physical Dimensions/Connection Diagrams
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*WS256N: A23-A0
WS128N: A22-A0
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Burst
State
Control
de
X-Decoder
Cell Matrix
Burst
Address
Counter
Page 5 of 79
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