Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
EZ-PD CCG4
USB Type-C Port Controller
EZ-PD CCG4, USB Type-C Port Controller
General Description
EZ-PD™ CCG4 is a dual USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG4 provides
a complete dual USB Type-C and USB-Power Delivery port control solution for notebooks, power adapters and docking stations. It
can also be used in dual role and downstream facing port applications. EZ-PD CCG4 uses Cypress’s proprietary M0S8 technology
with a 32-bit, 48-MHz Arm
®
Cortex
®
-M0 processor with 128 KB flash and integrates two complete Type-C Transceivers including the
Type-C termination resistors R
P
and R
D
.
Applications
Notebooks
■
Power adapters
■
Docking stations
■
■
■
■
■
Features
32-bit MCU Subsystem
48-MHz Arm Cortex-M0 CPU
■
128-KB Flash
■
8-KB SRAM
■
Integrated dead battery termination for DRP (Power
Source/Sink) applications
Supports two USB Type-C ports
Integrated VCONN FETs to power EMCA cables
Integrated fast role swap and extended data messaging (not
supported for 33-ball CSP part)
2.7-V to 5.5-V operation
Independent supply voltage pin for GPIO that allows 1.71-V to
5.5-V signaling on the I/Os
Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.5 mA
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C (on 40-pin QFN and 33-ball CSP
only)
Low-Power Operation
■
■
■
Integrated Digital Blocks
Up to four integrated timers and counters to meet response
times required by the USB-PD protocol
■
Four run-time serial communication blocks (SCBs) with
re-configurable I
2
C, SPI, or UART functionality
■
System-Level ESD on CC Pins
■
Clocks and Oscillators
■
Hot Swappable I/Os
■
Integrated oscillator eliminating the need for external clock
Port 0 I
2
C pins and CC1, CC2 pins are hot-swappable
4.0 mm
4.0 mm, 0.5 mm, 24-pin QFN
6.0 mm
6.0 mm, 0.6 mm, 40-pin QFN
2.4 mm x 2.5 mm, 0.5 mm, 33-ball CSP
Supports extended industrial temperature range
(–40 °C to +105 °C)
Type-C and USB-PD Support
Integrated USB Power Delivery 3.0 support (only PD 2.0
support for 33-ball CSP part)
■
Two integrated USB-PD BMC transceivers
[1]
[2]
■
Integrated UFP (R
D
) and current sources for DFP (R
P
) on
both Type-C ports
■
Packages
■
■
■
■
Notes
1. UFP refers to Power Sink.
2. DFP refers to Power Source.
Cypress Semiconductor Corporation
Document Number: 001-98440 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 8, 2020
EZ-PD CCG4
Logic Block Diagram
CCG4: Single-Chip Type-C Controller
MCU Subsystem
Integrated Digital Blocks
4 x TCPWM
1
M
Programmable I/O Matrix
I/O Subsystem
CC_PORT0
5
CC_PORT1
5
2x V
CONN
FETs
(PORT0)
2x V
CONN
FETs
(PORT1)
GPIOs
6
CORTEX-M0
48 MHz
Advanced High-Performance Bus (AHB)
4 x SCB
2
(I
2
C, SPI, UART)
Profiles and
Configurations
2 x Baseband MAC
Flash
(128KB)
2 x Baseband PHY
SRAM
(8KB)
Integrated R
d3
and R
p4
4 x 8-bit SAR ADC
Serial Wire Debug
1.
2.
3.
4.
5.
6.
Timer, counter, pulse width modulation block
Serial communication block configurable as UART, SPI, or I
2
C
Termination resistor denoting a UFP
Current sources to indicate a DFP
Configuration channel
General purpose input/output
Document Number: 001-98440 Rev. *M
Page 2 of 38
EZ-PD CCG4
Contents
Available Firmware and Software Tools ......................... 4
EZ-PD Configuration Utility ......................................... 4
EZ-PD CCG4 Block Diagram ............................................ 4
Functional Overview ........................................................ 5
CPU and Memory Subsystem ..................................... 5
USB-PD Subsystem (SS) ............................................ 5
System Resources ...................................................... 6
Peripherals .................................................................. 7
GPIO ........................................................................... 7
Pinouts .............................................................................. 8
Power ............................................................................... 18
Application Diagrams ..................................................... 19
Electrical Specifications ................................................ 21
Absolute Maximum Ratings ....................................... 21
Device-Level Specifications ...................................... 22
Digital Peripherals ..................................................... 24
Memory ..................................................................... 26
System Resources .................................................... 26
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Packaging ........................................................................ 30
Acronyms ........................................................................ 33
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
References and Links to Applications Collaterals ...... 35
Knowledge Base Articles ........................................... 35
Application Notes ...................................................... 35
Reference Designs .................................................... 35
Kits ............................................................................ 35
Datasheets ................................................................ 35
Document History Page ................................................. 36
Sales, Solutions, and Legal Information ...................... 38
Worldwide Sales and Design Support ....................... 38
Products .................................................................... 38
PSoC® Solutions ...................................................... 38
Cypress Developer Community ................................. 38
Technical Support ..................................................... 38
Document Number: 001-98440 Rev. *M
Page 3 of 38
EZ-PD CCG4
Available Firmware and Software Tools
EZ-PD Configuration Utility
The EZ-PD Configuration Utility is a GUI-based Microsoft Windows application developed by Cypress to guide a CCGx user through
the process of configuring and programming the chip. The utility allows users to:
1. Select and configure the parameters they want to modify
2. Program the resulting configuration onto the target CCGx device.
The utility works with the Cypress supplied CCG1, CCG2, CCG3, and CCG4 kits, which host the CCGx controllers along with a USB
interface. This version of the EZ-PD Configuration Utility supports configuration and firmware update operations on CCGx controllers
implementing EMCA and Display Dongle applications. Support for other applications, such as Power Adapters and Notebook port
controllers, will be provided in later versions of the utility.
You can download the EZ-PD Configuration Utility and its associated documentation at the following link:
http://www.cypress.com/documentation/software-and-drivers/ez-pd-configuration-utility
EZ-PD CCG4 Block Diagram
Figure 1. EZ-PD CCG4 Block Diagram
CPU Subsystem
CCG4
32-bit
SWD/TC
SPCIF
Cortex
M0
48 MHz
FAST MUL
NVIC, IRQMX
FLASH
128 KB
Read Accelerator
SRAM
8 KB
SRAM Controller
ROM
8 KB
ROM Controller
AHB-Lite
System Resources
Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
Clock
Clock Control
WDT
IMO
ILO
System Interconnect (Single Layer AHB)
Peripherals
PCLK
Peripheral Interconnect (MMIO)
2 x USB-PD 3.0
IOSS GPIO
(5 x ports)
4 x TCPWM
4 x SCB
Reset
Reset Control
XRES
Test
DFT Logic
DFT Analog
Power Modes
Active/Sleep
Deep Sleep
High Speed I/O Matrix
27 x GPIOs, 2 OVTs
Pads, ESD
I/O Subsystem
Document Number: 001-98440 Rev. *M
2 X VCONN FET
2 x SAR ADC
CC BB PHY
Page 4 of 38
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