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CY7C1061G/CY7C1061GE
16-Mbit (1M words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1M words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
High speed
❐
t
AA
= 10 ns/15 ns
Embedded error-correcting code (ECC) for single-bit error
correction
[1, 2]
Low active and standby currents
❐
I
CC
= 90 mA typical at 100 MHz
❐
I
SB2
= 20 mA typical
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
1.0 V data retention
Transistor-transistor logic (TTL) compatible inputs and outputs
Error indication (ERR) pin to indicate 1-bit error detection and
correction
Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball
VFBGA packages
To access devices with a single chip enable input, assert the chip
enable (CE) input LOW. To access dual chip enable devices,
assert both chip enable inputs – CE
1
as LOW and CE
2
as HIGH.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O
0
through I/O
15
) and address pins (A
0
through A
19
) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O
8
through
I/O
15
and BLE controls I/O
0
through I/O
7
.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O
0
through I/O
15
). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O
0
through I/O
15
) are placed in a high-impedance state
when the device is deselected (CE HIGH for a single chip enable
device and CE
1
HIGH / CE
2
LOW for a dual chip enable device),
or control signals are de-asserted (OE, BLE, BHE).
On the CY7C1061GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the
Truth Table
on page 16
for a complete description of read and write modes.
The logic block diagrams are on page 2.
The CY7C1061G and CY7C1061GE devices are available in
48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.
For a complete list of related documentation, click
here.
■
■
■
■
■
■
■
Functional Description
CY7C1061G and CY7C1061GE are high-performance CMOS
fast static RAM devices with embedded ECC
[1]
. Both devices are
offered in single and dual chip enable options and in multiple pin
configurations. The CY7C1061GE device includes an ERR pin
that signals a single-bit error-detection and correction event
during a read cycle.
Product Portfolio
Current Consumption
Product
Features and Options
(see
Pin Configurations on
page 4)
Single or dual chip enables
Optional ERR pins
Address MSB A
19
pin
placement options
compatible with Cypress and
other vendors
Range
V
CC
Range
(V)
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
Speed Operating I
CC
, (mA)
(ns)
f = f
max
10/15
Typ
[3]
Max
15
10
10
70
90
90
80
110
110
Standby, I
SB2
(mA)
Typ
[3]
20
Max
30
CY7C1061G18
CY7C1061G(E)30
CY7C1061G
Industrial
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer
AN88889
for details.
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for a V
CC
range of 1.65 V–2.2 V),
V
CC
= 3 V (for a V
CC
range of 2.2 V–3.6 V), and V
CC
= 5 V (for a V
CC
range of 4.5 V–5.5 V), T
A
= 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-81540 Rev. *T
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised July 13, 2018
CY7C1061G/CY7C1061GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads and Waveforms ....................................... 8
Data Retention Characteristics ....................................... 9
Data Retention Waveform ................................................ 9
AC Switching Characteristics ....................................... 10
Switching Waveforms .................................................... 11
Truth Table ...................................................................... 16
ERR Output – CY7C1061GE .......................................... 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 001-81540 Rev. *T
Page 3 of 25
CY7C1061G/CY7C1061GE
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout,
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout,
Dual Chip Enable without ERR, Address MSB A19 at Ball G2, Dual Chip Enable without ERR, Address MSB A19 at Ball H6,
CY7C1061G
[4]
Package/Grade ID: BVJXI
CY7C1061G
[4]
Package/Grade ID: BVXI
1
BLE
I/O8
I/O9
2
OE
BHE
I/O10
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
1
I/O1
I/O3
I/O4
I/O5
WE
A11
6
CE
2
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NC
A
B
C
D
E
F
G
H
1
BLE
I/O8
I/O9
2
OE
BHE
I/O10
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
1
I/O1
I/O3
I/O4
I/O5
WE
A11
6
CE
2
I/O0
I/O2
VCC
VSS
I/O6
I/O7
A
19
A
B
C
D
E
F
G
H
VSS I/O11
VCC
I/O12
VSS I/O11
VCC
I/O12
I/O14 I/O13
I/O15
A18
A19
A8
I/O14 I/O13
I/O15
A18
NC
A8
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout, Single Chip Enable without ERR, Address MSB A19 at Ball G2, CY7C1061G
[4]
Package/Grade ID: BV1XI
Note
4. NC pins are not connected internally to the die.
Document Number: 001-81540 Rev. *T
Page 4 of 25
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