CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
36-Mbit (1M × 36/2M × 18)
Pipelined SRAM
with NoBL™ Architecture (With ECC)
36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC)
Features
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Functional Description
The CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are 2.5 V, 1M × 36/2M × 18 synchronous
pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic,
respectively. They are designed to support unlimited true
back-to-back read/write operations with no wait states. The
CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/
CY7C1462KVE25 are equipped with the advanced NoBL logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data in systems that require frequent
write/read transitions. The CY7C1460KV25/CY7C1462KV25/
CY7C1460KVE25/CY7C1462KVE25 are pin-compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle. Write operations are controlled by the byte write selects
for
CY7C1460KV25/CY7C1460KVE25
and
BW
a
–BW
d
BW
a
–BW
b
for CY7C1462KV25/CY7C1462KVE25 and a write
enable (WE) input. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Pin-compatible and functionally equivalent to ZBT™
Supports 250 MHz bus operations with zero wait states
❐
Available speed grades are 250 MHz, 200 MHz, and 167 MHz
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte Write capability
2.5 V core power supply
2.5 V I/O power supply
Fast clock-to-output times
❐
2.5 ns (for 250 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self-timed writes
CY7C1460KV25, CY7C1462KV25, CY7C1460KVE25 and
CY7C1462KVE25 available in JEDEC-standard Pb-free
100-pin TQFP, and Pb-free and non Pb-free 165-ball FBGA
packages.
IEEE 1149.1 JTAG-Compatible Boundary Scan
Burst capability — linear or interleaved burst order
“ZZ” sleep mode option
On-chip error correction code (ECC) to reduce soft error rate
(SER)
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Selection Guide
Description
Maximum access time
Maximum operating current
× 18
× 36
250 MHz
2.5
220
240
200 MHz
3.2
190
210
167 MHz
3.4
170
190
Unit
ns
mA
Cypress Semiconductor Corporation
Document Number: 001-66679 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 7, 2018
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Logic Block Diagram – CY7C1460KV25
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
a
DQP
b
DQP
c
DQP
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Logic Block Diagram – CY7C1462KV25
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
BURST A0'
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP
a
DQP
b
E
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Document Number: 001-66679 Rev. *J
Page 2 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Logic Block Diagram – CY7C1460KVE25
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
C
C
D
E
C
O
D
E
R
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
E
ECC
ENCODER
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Document Number: 001-66679 Rev. *J
Page 3 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Logic Block Diagram – CY7C1462KVE25
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
A
BW
B
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
C
C
D
E
C
O
D
E
R
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQP
A
DQP
B
E
E
ECC
ENCODER
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Document Number: 001-66679 Rev. *J
Page 4 of 32
CY7C1460KV25/CY7C1462KV25
CY7C1460KVE25/CY7C1462KVE25
Contents
Pin Configurations ........................................................... 6
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Burst Read Accesses .................................................. 9
Single Write Accesses ............................................... 10
Burst Write Accesses ................................................ 10
Sleep Mode ............................................................... 10
On-Chip ECC ............................................................ 10
Interleaved Burst Address Table ............................... 11
Linear Burst Address Table ....................................... 11
ZZ Mode Electrical Characteristics ............................ 11
Truth Table ...................................................................... 12
Partial Write Cycle Description ..................................... 13
Partial Write Cycle Description ..................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port (TAP) ............................................. 14
PERFORMING A TAP RESET .................................. 14
TAP REGISTERS ...................................................... 14
TAP Instruction Set ................................................... 15
TAP Controller State Diagram ....................................... 16
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 16
TAP AC Switching Characteristics ............................... 17
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent ......................... 18
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Document Number: 001-66679 Rev. *J
Page 5 of 32
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