Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
FM25640B
64-Kbit (8K × 8) Serial (SPI) F-RAM
64-Kbit (8K × 8) Serial (SPI) F-RAM
Features
■
Functional Description
The FM25640B is a 64-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 151 years
while eliminating the complexities, overhead, and system level
reliability problems caused by serial flash, EEPROM, and other
nonvolatile memories.
Unlike serial flash and EEPROM, the FM25640B performs write
operations at bus speed. No write delays are incurred. Data is
written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The FM25640B is capable of supporting
10
14
read/write cycles, or 100 million times more write cycles
than EEPROM.
These capabilities make the FM25640B ideal for nonvolatile
memory applications requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The FM25640B provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
FM25640B uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
specifications are guaranteed over an industrial temperature
range of –40
C
to +85
C.
For a complete list of related documentation, click
here.
64-Kbit ferroelectric random access memory (F-RAM) logically
organized as 8K × 8
14
❐
High-endurance 100 trillion (10 ) read/writes
❐
151-year data retention (See
Data Retention and Endurance
on page 12)
❐
NoDelay™ writes
❐
Advanced high-reliability ferroelectric process
Very fast serial peripheral interface (SPI)
❐
Up to 20 MHz frequency
❐
Direct hardware replacement for serial flash and EEPROM
❐
Supports SPI mode 0 (0, 0) and mode 3 (1, 1)
Sophisticated write protection scheme
❐
Hardware protection using the Write Protect (WP) pin
❐
Software protection using Write Disable instruction
❐
Software block protection for 1/4, 1/2, or entire array
Low power consumption
❐
250
A
active current at 1 MHz
❐
4
A
(typ) standby current
Voltage operation: V
DD
= 4.5 V to 5.5 V
Industrial temperature: –40
C
to +85
C
8-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
■
■
■
■
■
■
■
Logic Block Diagram
WP
CS
HOLD
SCK
Instruction Decoder
Clock Generator
Control Logic
Write Protect
8Kx8
F-RAM Array
Instruction Register
Address Register
Counter
SI
13
8
Data
I/
O Register
3
Nonvolatile Status
Register
SO
Cypress Semiconductor Corporation
Document Number: 001-84468 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 6, 2018
FM25640B
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 4
Memory Architecture ........................................................ 4
Serial Peripheral Interface – SPI Bus .............................. 4
SPI Overview ............................................................... 4
SPI Modes ................................................................... 5
Power Up to First Access ............................................ 6
Command Structure .................................................... 6
WREN - Set Write Enable Latch ................................. 6
WRDI - Reset Write Enable Latch ............................... 6
Status Register and Write Protection ............................. 6
RDSR - Read Status Register ..................................... 7
WRSR - Write Status Register .................................... 7
Memory Operation ............................................................ 8
Write Operation ........................................................... 8
Read Operation ........................................................... 8
HOLD Pin Operation ................................................... 9
Endurance ................................................................. 10
Maximum Ratings ........................................................... 11
Operating Range ............................................................. 11
DC Electrical Characteristics ........................................ 11
Data Retention and Endurance ..................................... 12
Capacitance .................................................................... 12
Thermal Resistance ........................................................ 12
AC Test Conditions ........................................................ 12
AC Switching Characteristics ....................................... 13
Power Cycle Timing ....................................................... 15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagram ............................................................ 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Document History Page ................................................. 19
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC® Solutions ...................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Document Number: 001-84468 Rev. *I
Page 2 of 21
FM25640B
Pinout
Figure 1. 8-pin SOIC pinout
CS
1
2
3
4
Top View
not to scale
8
7
6
5
VDD
HOLD
SCK
SI
SO
WP
VSS
Pin Definitions
Pin Name
CS
I/O Type
Input
Description
Chip Select.
This active LOW input activates the device. When HIGH, the device enters low-power
standby mode, ignores other inputs, and tristates the output. When LOW, the device internally
activates the SCK signal. A falling edge on CS must occur before every opcode.
Serial Clock.
All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge
and outputs occur on the falling edge. Because the device is synchronous, the clock frequency may
be any value between 0 and 20 MHz and may be interrupted at any time.
Serial Input.
All data is input to the device on this pin. The pin is sampled on the rising edge of SCK
and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications.
Serial Output.
This is the data output pin. It is driven during a read and remains tristated at all other
times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock.
Write Protect.
This active LOW pin prevents write operation to the Status Register when WPEN is
set to ‘1’. This is critical because other write protection features are controlled through the Status
Register. A complete explanation of write protection is provided in
Status Register and Write Protection
on page 7.
This pin must be tied to V
DD
if not used. Note that the function of WP is different from the
FM25040 where it prevents all writes to the part.
HOLD Pin.
The HOLD pin is used when the host CPU must interrupt a memory operation for another
task. When HOLD is LOW, the current operation is suspended. The device ignores any transition on
SCK or CS. All transitions on HOLD must occur while SCK is LOW. This pin must be tied to V
DD
if not
used.
SCK
Input
SI
[1]
SO
[1]
WP
Input
Output
Input
HOLD
Input
V
SS
V
DD
Power supply Ground for the device. Must be connected to the ground of the system.
Power supply Power supply inputs to the device.
Note
1. SI may be connected to SO for a single pin data interface
.
Document Number: 001-84468 Rev. *I
Page 3 of 21
FM25640B
Functional Overview
The FM25640B is a serial F-RAM memory. The memory array is
logically organized as 8,192 × 8 bits and is accessed using an
industry standard serial peripheral interface (SPI) bus. The
functional operation of the F-RAM is similar to serial flash and
serial EEPROMs. The major difference between the FM25640B
and a serial flash or EEPROM with the same pinout is the
F-RAM's superior write performance, high endurance, and low
power consumption.
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated, the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms in the SPI protocol are as follows:
SPI Master
The SPI master device controls the operations on a SPI bus. An
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
of the operations must be initiated by the master activating a
slave device by pulling the CS pin of the slave LOW. The master
also generates the SCK and all the data transmission on SI and
SO lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. An SPI slave never initiates a communication on the SPI
bus and acts only on the instruction from the master.
The FM25640B operates as an SPI slave and may share the SPI
bus with other SPI slave devices.
Chip Select (CS)
To select any slave device, the master needs to pull down the
corresponding CS pin. Any instruction can be issued to a slave
device only while the CS pin is LOW. When the device is not
selected, data through the SI pin is ignored and the serial output
pin (SO) remains in a high-impedance state.
Note
A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
The Serial Clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
The FM25640B enables SPI modes 0 and 3 for data
communication. In both of these modes, the inputs are latched
by the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of a SPI instruction on
the SI pin. Further, all data inputs and outputs are synchronized
with SCK.
Data Transmission (SI/SO)
The SPI data bus consists of two lines, SI and SO, for serial data
communication. SI is also referred to as Master Out Slave In
(MOSI) and SO is referred to as Master In Slave Out (MISO). The
master issues instructions to the slave through the SI pin, while
Page 4 of 21
Memory Architecture
When accessing the FM25640B, the user addresses 8K
locations of eight data bits each. These eight data bits are shifted
in or out serially. The addresses are accessed using the SPI
protocol, which includes a chip select (to permit multiple devices
on the bus), an opcode, and a two-byte address. The upper 3 bits
of the address range are 'don't care' values. The complete
address of 13 bits specifies each byte address uniquely.
Most functions of the FM25640B are either controlled by the SPI
interface or handled by on-board circuitry. The access time for
the memory operation is essentially zero, beyond the time
needed for the serial protocol. That is, the memory is read or
written at the speed of the SPI bus. Unlike a serial flash or
EEPROM, it is not necessary to poll the device for a ready
condition because writes occur at bus speed. By the time a new
bus transaction can be shifted into the device, a write operation
is complete. This is explained in more detail in the interface
section.
Note
The FM25640B contains no power management circuits
other than a simple internal power-on reset circuit. It is the user’s
responsibility to ensure that V
DD
is within datasheet tolerances
to prevent incorrect operation. It is recommended that the part is
not powered down with chip enable active.
Serial Peripheral Interface – SPI Bus
The FM25640B is a SPI slave device and operates at speeds up
to 20 MHz. This high-speed serial bus provides
high-performance serial communication to a SPI master. Many
common microcontrollers have hardware SPI ports allowing a
direct interface. It is quite simple to emulate the port using
ordinary port pins for microcontrollers that do not. The
FM25640B operates in SPI Mode 0 and 3.
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
The SPI is a synchronous serial interface, which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on the SPI bus is activated using the CS
pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both of these modes, data is clocked into the F-RAM on the rising
Document Number: 001-84468 Rev. *I
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
