TR
SYN C SRA M
TO
IT
CHSCREE N
ECC
A
U ETOU CH
W
U
H ON -CHIP
SOLUTIONS
COMPLETE FREEDOM
FROM SOFT ERRORS
ASYNCHRONOUS SRAMS WITH
ERROR-CORRECTING CODE (ECC)
SOFT ERROR: HOW BAD IS IT?
With every new process technology node there is significant improvement in performance and power consumption
along with reduction in the size of the chip. Each new process technology reduces voltage and shrinks the
capacitance of the node. This reduced node capacitance make these devices more susceptible to bit failures
caused by energetic particles. These bit failures are called soft errors.
Electronic devices are frequently exposed to extraterrestrial energetic particles like Alpha particles,
Cosmic rays & Thermal neutrons. With today’s advanced process nodes, memories are highly likely to
fail due to soft errors caused by this extraterrestrial radiation.
Soft errors not only corrupt data, but can also lead to loss of function and system critical failures.
Industrial controllers, military equipment, networking systems, medical devices, automotive
electronics, and consumer electronics are especially vulnerable to the adverse effects of soft
errors. An uncorrected soft error can lead to system failures in mission critical industrial
automation, automotive engine control, and high-end security systems.
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async.cypress.com
A SYN C SRA M W IT H ON -CHIP ECC
WHAT’S THE SOLUTION?
Soft errors are usually dealt with through redundancy &
software. Redundancy involves storing the same data on
multiple chips to insure against data loss. It’s quite expensive
and takes up a lot of board space. While software doesn’t
take up extra board space, it is tedious, expensive and time
consuming. Both these solutions are impractical in latest
generation devices due to board space and product cycle
time restrictions.
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COMPLETE FREEDOM FROM SOFT ERRORS
Cypress’ Asynchronous SRAM with On-Chip Error Correcting Code (ECC) provides a faster, simpler and
more cost effective solution than software or redundancy based ECC schemes. It is the industry’s highest
reliability chip, built to service a wide variety of applications.
ERROR CORRECTING CODE (ECC)
BIT-INTERLEAVING
Cypress’s latest generation Asynchronous SRAM
devices use (38,32) Hamming Code for single-bit
error detection and correction using ECC. The
hardware ECC block in Cypress’ ultra-reliable
Asynchronous SRAMs performs all ECC related
functions in line, without user intervention.
Higher energy extraterrestrial radiation can flip
multiple adjacent bits, leading to multi-bit errors.
The single-bit error detection and correction
capability of Error Correcting Code is
supplemented by a bit-interleaving scheme to
prevent the occurrence of multi-bit errors.
Together, these features provide significant improvement in Soft Error Rate (SER) performance, resulting
in industry leading FIT rates less than 0.1 FIT/Mbit.
Embedded ECC to
detect and correct
all single-bit errors
Bit-interleaving to
avoid multi-bit upsets
Optional ERR pin to
indicate the occurrence
of single-bit error
Industry leading access
time: 10 ns (FAST)
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async.cypress.com
A SYN C SRA M W IT H ON -CHIP ECC
Address Bus
(19 - 21)
Data Bus
(x8/x16/ x32)
Address
Decoder
Memory Array
512K x 19 bit
(16 data bits and 3
parity bits)
ECC
Encoder
Sense
AMPS
Input
Buffer
ECC
ECC
Encoder
I/O MUX
ERR
Control
Circuit
CE, OE, WE,
BHE, BLE
ASYNCHRONOUS SRAM WITH ON-CHIP ECC FAMILY
PARAMETERS
ACCESS TIME
4- M
bIT
F
aST
SRaM
10 ns
4-M
bIT
L
Ow
P
OwER
SRaM
45 ns
20 mA
8.7 µA
4- M
bIT
F
aST
SRaM
wITH
P
OwER
S
N OOzE
™
10 ns
45 mA
15 µA
16 - M
bIT
F
aST
SRaM
10 ns
110 mA
30 mA
16 - M
bIT
L
Ow
P
OwER
SRaM
45 ns
36 mA
16 µA
16 - M
bIT
F
aST
SRaM
wITH
P
OwER
S
N OOzE
™
10 ns
110 mA
22 µA
OPERATING CURRENT (MAX.)
45 mA
STANDBY CURRENT (MAX.)
8 mA
Ultra-low standby
current: 8.7 µA
(4-Mbit MoBL)
Multiple configurations
(x8, x16, and x32) and
operating voltages
(1.8V, 3V, 5V)
Available in industrial
and automotive
temperature grades
Form-fit-function
compatible with current
generation ASYNC
SRAM devices
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