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The fact that Infineon offers the following product as part of the Infineon product
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Infineon continues to support existing part numbers. Please continue to use the
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CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
HX3 USB 3.0 Hub
HX3 USB 3.0 Hub
General Description
HX3 is a family of USB 3.0 hub controllers compliant with the USB 3.0 specification revision 1.0. HX3 supports SuperSpeed (SS),
Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. It has integrated termination, pull-up, and pull-down resistors,
and supports configuration options through pin-straps to reduce the overall BOM of the system.
HX3 includes the following Cypress-proprietary features:
Shared Link™:
Enables extra downstream (DS) ports for on-board connections in embedded applications
Ghost Charge™:
Enables charging of devices connected to the DS ports when no host is connected on the upstream (US) port
HX3 USB 3.0 Hub
Features
■
■
■
USB-IF Certified Hub, TID# 330000060, 30000074
Supports up to Four USB 3.0-Compliant DS ports
❐
All ports support SS (5 Gbps), and are backward-compatible
with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)
❐
SS and USB 2.0 Link Power Management (LPM)
❐
Dedicated Hi-Speed Transaction Translators (Multi-TT)
❐
LED status indicators – suspend, SS, and USB 2.0 operation
Shared Link™ for Embedded Applications
❐
Each DS port can simultaneously connect to an embedded
SS device and a removable USB 2.0 device
❐
Enables up to eight device connections
Enhanced Battery Charging
❐
Each DS port complies with the USB Battery Charging v1.2
(BC v1.2) specification
❐
Ghost Charge™: Each DS port can emulate a Dedicated
Charging Port (DCP) when the host is not connected to the
US port
❐
Accessory Charger Adapter Dock (ACA-Dock): Enables
charging and simultaneous data transfer for a smart phone
or a tablet acting as a host compliant to BC v1.2
❐
Apple charging supported on all DS ports
Integrated ARM
®
Cortex™-M0 CPU
❐
16 KB RAM, 32 KB ROM
❐
Configure GPIOs for overcurrent protection, power enable,
and LEDs
2
❐
Upgrade firmware using (a) I C EEPROM or (b) an external
2
I C master
Vendor-Command Support to Implement a USB-to-I
2
C Bridge
❐
Firmware upgrade of an external ASSP connected to HX3
through USB
❐
In-System Programming (ISP) of the EEPROM connected to
HX3 through USB
Extensive Configuration Support
❐
Pin-strap configuration for the following functions:
• Vendor ID (VID)
• Charging support for each DS port
• Number of active ports
• Number of non-removable devices
• Ganged or individual power switch enables for DS ports
• Power switch polarity selection
2
❐
Custom configuration modes supported with eFuse, I C
2
C slave
EEPROM, or I
• SS and USB 2.0 PHY parameters
• Product ID (PID)/VID, manufacturer, and product string
descriptors
• Swap DP/DM signals for flexible PCB routing
Software Features
❐
Microsoft WHQL-certified for Windows XP/Vista/7/8/8.1
❐
Compatible with Mac OS 10.9 and Linux kernel version 3.11
❐
Customize configuration parameters with the easy-to-use
Cypress’s “Blaster Plus” software tool
Flexible Packaging Options
❐
68-pin QFN (8 × 8 × 1.0 mm)
❐
88-pin QFN (10 × 10 × 1.0 mm)
❐
100-ball BGA (6 × 6 × 1.0 mm)
❐
Industrial temperature range (–40 °C to +85 °C)
■
■
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 001-73643 Rev. *T
•
198 Champion Court
•
San Jose
,
CA 95134-1709
• +1-408-943-2600
Revised April 30, 2019
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Block Diagram
US Port
SSRxP/M
SSTxP/M
VBUS
DP
DM
USB 2.0
SS
USB 2.0
PHY
USB 2.0 Controller
SS
PHY
VBUS
Detect
SS Controller
ARM
Cortex-M0
RAM
ROM
I2C
I2C_DATA
I2C_CLK
PHY Interface
Hub Controller
Four Transaction
Translators
US Port Control Routing
Hub Controller
3.3 V
1.2 V
Repeater
US Buffers
DS Buffers
PLL
26 MHz
Routing Logic
Buffer and Routing Logic
USB 2.0
PHY
SS
PHY
Port
Control
USB 2.0
PHY
SS
PHY
Port
Control
USB 2.0
PHY
SS
PHY
Port
Control
USB 2.0
PHY
SS
PHY
Port
Control
SSRxP/M
SSTxP/M
SSTxP/M
SSTxP/M
SSRxP/M
SSRxP/M
SSRxP/M
SSTxP/M
PWR
OVR
LED
PWR
OVR
LED
PWR
OVR
LED
DP
DM
DP
DM
DP
DM
DS Port 1
DS Port 2
DS Port 3
DP
DM
DS Port 4
Document Number: 001-73643 Rev. *T
PWR
OVR
LED
Page 2 of 45
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Contents
Architecture Overview ..................................................... 4
SS Hub Controller ....................................................... 4
USB 2.0 Hub Controller ............................................... 4
CPU ............................................................................. 4
I2C Interface ................................................................ 4
Port Controller ............................................................. 4
Applications ...................................................................... 4
HX3 Product Options ....................................................... 5
Product Features .............................................................. 6
Shared Link ................................................................. 6
Ghost Charge .............................................................. 6
Vendor-Command Support ......................................... 7
ACA-Dock Support ...................................................... 7
Pin Information ................................................................. 8
System Interfaces ........................................................... 24
Upstream Port (US) ................................................... 24
Downstream Ports (DS1, 2, 3, 4) .............................. 24
Communication Interfaces (I2C) ................................ 24
Oscillator ................................................................... 24
GPIOs ........................................................................ 24
Power Control ............................................................ 24
Reset ......................................................................... 24
Configuration Mode Select ........................................ 24
Configuration Options ................................................ 25
EMI ................................................................................... 33
ESD .................................................................................. 33
Absolute Maximum Ratings .......................................... 34
Electrical Specifications ................................................ 34
DC Electrical Characteristics ..................................... 34
Power Consumption .................................................. 35
Ordering Information ...................................................... 36
Ordering Code Definitions ......................................... 37
Packaging ........................................................................ 38
Package Diagrams .......................................................... 39
Acronyms ........................................................................ 41
Reference Documents .................................................... 41
Document Conventions ................................................. 41
Units of Measure ....................................................... 41
Silicon Revision History ................................................ 42
Method of Identification ............................................. 42
Document History Page ................................................. 43
Sales, Solutions, and Legal Information ...................... 45
Worldwide Sales and Design Support ....................... 45
Products .................................................................... 45
PSoC® Solutions ...................................................... 45
Cypress Developer Community ................................. 45
Technical Support ..................................................... 45
Document Number: 001-73643 Rev. *T
Page 3 of 45
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Architecture Overview
The
Block Diagram on page 2
shows the HX3 architecture. HX3
consists of two independent hub controllers (SS and USB 2.0),
the Cortex-M0 CPU subsystem, an I
2
C interface, and port
controller blocks.
I
2
C Interface
The I
2
C interface in HX3 supports the following:
■
SS Hub Controller
This block supports the SS hub functionality based on the
USB 3.0 specification. The SS hub controller supports the
following:
■
■
I
2
C Slave, Master, and Multi-master configurations
2
2
❐
Configure HX3 by an external I C master in I C slave mode
2
❐
Configure HX3 from an I C EEPROM
2
❐
Multi-master mode to share EEPROM with other I C masters
In-System Programming of the I
2
C EEPROM from HX3’s
US port
■
Port Controller
The port controller block controls DS port power to comply with
the BC v1.2 and USB 3.0 specifications. This block also controls
the US port power in the ACA-Dock mode. Control signals for
external power switches are implemented within the chip. HX3
controls the external power switches at power-on to reduce
in-rush current.
The port controller block supports the following:
■
■
■
■
SS link power management (U0, U1, U2, U3 states)
Full-duplex data transmission
USB 2.0 Hub Controller
This block supports the LS, FS, and HS hub functionalities. It
includes the repeater, frame timer, and four transaction trans-
lators.
The USB 2.0 hub controller block supports the following:
■
■
■
Overcurrent detection
SS and USB 2.0 port indicators for each DS port
Ganged and individual power control modes
Automatic port numbering based on active ports
USB 2.0 link power management (L0, L1, L2, L3 states)
Suspend, resume, and remote wake-up signaling
Multi-TT (one TT for each DS port)
CPU
The ARM Cortex-M0 CPU subsystem is used for the following
functions:
■
■
■
■
■
■
Applications
■
■
■
■
■
■
■
■
Standalone hubs
PC and tablet motherboards
Docking station
Hand-held cradles
Monitors
Digital TVs
Set-top boxes
Printers
System configuration and initialization
Battery charging control
Vendor-specific commands for the USB-to-I
2
C bridge
String-descriptor support
Suspend status indicator
Shared Link support in embedded systems
Document Number: 001-73643 Rev. *T
Page 4 of 45
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