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ordering part number with the prefix “CY”.
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
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MB90911AS/F912BS/V950AMAS
F
2
MC-16LX MB90910 Series
16-bit Microcontroller
The MB90910 series, loaded 1 channel FULL-CAN controller and Flash ROM, is general-purpose Cypress 16-bit microcontroller
designing for automotive and industrial applications. Its main feature is the on-board CAN controllers, which conform to Ver 2.0 Part
A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN
approach. With the new 0.18
m CMOS technology, Cypress now offers on-chip Flash ROM program memory up to 128 Kbytes.
The power supply (1.8 V) is supplied to the MCU core from an internal regulator circuit. This creates a major advantage in terms of
EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 31.25 ns instruction execution time from an external 4 MHz clock.
The unit features a 4-channel input capture unit 1 channel 16-bit free-run timer, 2-channel LIN-UART,
1-channel UART, and 16-channel 8/10-bit A/D converter as the peripheral resource.
Features
Clock
■
■
Low power consumption (standby) mode
■
■
■
■
■
Built-in PLL clock frequency multiplication circuit
Selection of machine clocks (PLL clocks) is allowed among
frequency division by 2 on oscillation clock and multiplication
of 1 to 8 times of oscillation clock (for 4 MHz oscillation clock,
4 MHz to 32 MHz)
Minimum execution time of instruction : 31.25 ns (when
operating with 4-MHz oscillation clock and 8-time multiplied
PLL clock)
Sleep mode (a mode that halts CPU operating clock)
Main timer mode (timebase timer mode that is transferred
from main clock mode)
PLL timer mode (timebase timer mode that is transferred from
PLL clock mode)
Stop mode (a mode that stops oscillation clock)
CPU blocking operation mode
■
Instruction system best suited to controller
■
■
■
■
■
■
Process
CMOS technology
16 Mbytes CPU memory space
24-bit internal addressing
Wide choice of data types (bit, byte, word, and long word)
Wide choice of addressing modes (23 types)
Enhanced multiply-divide instructions with sign and RETI
instructions
Enhanced high-precision computing with 32-bit accumulator
I/O port
General purpose input/output port (CMOS output) :
- 36 ports
Timer
■
■
■
■
Timebase timer, watchdog timer : 1 channel
8/16-bit PPG timer : 8-bit
6 channels or 16-bit
3 channels
16-bit reload timer : 2 channels
16- bit input/output timer
❐
-16-bit free-run timer : 1 channel (FRT0 : ICU 0/1/2/3)
❐
-16- bit input capture : (ICU) : 4 channels
Compliant with CAN specifications Version 2.0 Part A and B
16 message buffers are built in
CAN wake-up function
Instruction system compatible with high-level
language (C language) and multitask
■
■
■
Employing system stack pointer
Enhanced various pointer indirect instructions
Barrel shift instructions
FULL-CAN controller : 1 channel
■
■
■
Increased processing speed
4-byte instruction queue
Powerful interrupt function
■
■
Powerful 8-level, 34-condition interrupt feature
Up to 8 channels external interrupts are supported
UART (LIN/SCI) : LIN-UART2 channels, UART
1 channel
■
■
CPU-independent automatic data transfer func-
tion
Expanded intelligent I/O service function (EI
2
OS) : up to 16
channels
Equipped with full-duplex double buffer
Clock-asynchronous or clock-synchronous serial trans-
mission is available
Cypress Semiconductor Corporation
Document Number: 002-04578 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 12, 2016
MB90910 Series
DTP/External interrupt : up to 8 channels, CAN
wakeup : up to 1 channel
Module for activation of expanded intelligent I/O service (EI OS)
and generation of external interrupt by external input
2
Program patch function
Address matching detection for 6 address pointers
Capable of changing input voltage for port
Automotive/CMOS-Schmitt input level (initial level is Automotive
in single-chip mode)
Delay interrupt generator module
Generates interrupt request for task switching
ROM security function
The content of ROM can be protected (Only MASK ROM
product).
8/10-bit A/D converter : 16 channels
■
■
■
Resolution is selectable between 8-bit and 10-bit
Activation by external trigger input is allowed
Conversion time : 3
s (at 24 MHz machine clock, including
sampling time)
Flash memory security function
Protects the content of Flash memory
Document Number: 002-04578 Rev. *A
Page 2 of 64
MB90910 Series
Contents
Product Lineup ................................................................ 4
Pin Assignment ................................................................ 6
Pin Description ................................................................. 7
I/O Circuit Type .............................................................. 10
Handling Devices ............................................................ 15
Block Diagrams .............................................................. 18
Memory Map .................................................................... 20
I/O Map ............................................................................. 21
CAN Controllers .............................................................. 29
Interrupt Factors, Interrupt Vectors,
Interrupt Control Register .............................................. 36
Electrical Characteristics ............................................... 38
Absolute Maximum Ratings ....................................... 38
Recommended Conditions ........................................ 40
DC Characteristics .................................................... 41
AC Characteristics ..................................................... 43
Clock Timing .............................................................. 43
Reset Standby Input .................................................. 45
Power-on Reset ......................................................... 46
UART ......................................................................... 46
Trigger Input Timing .................................................. 51
Timer Related Resource Input Timing ....................... 52
Timer Related Resource Output Timing .................... 52
CAN PLL cycle jitter .................................................. 53
A/D Converter ............................................................ 54
Definition of A/D Converter Terms ........................... 56
Flash Memory Program/Erase Characteristics ......... 59
Ordering Information ..................................................... 60
Package Dimension ........................................................ 61
Major Changes .................................................................62
Document Number: 002-04578 Rev. *A
Page 3 of 64
MB90910 Series
1. Product Lineup
Part number
MB90V950AMAS
Parameter
Type
CPU
System clock
ROM
RAM
Emulator-specific
power supply*
1
FPGA data*
2
Adaptor board*
2
Technology
Operation voltage range
Operating ambient tem-
perature
Package
Evaluation product
Flash memory product
F
2
MC-16LX CPU
On-chip PLL clock multiplier (
1,
2,
3,
4,
6,
8, 1/2 when PLL stops)
Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL
8)
External
30 Kbytes
Yes
Rev 050617
MB2147-20 Rev.04C or later
0.35
m
CMOS with built-in power
supply regulator
5 V
10
128 Kbytes
8 Kbytes
64 Kbytes
4 Kbytes
MASK ROM product
MB90F912BS
MB90911AS
0.18
m
CMOS with built-in power supply regulator
3.0 V to 5.5 V : When normal operating
40
°C to
105
°C
LQFP-48
LIN-UART
2 channels, UART
1 channel
PGA-299
LIN-UART
7 channels
UART
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device (Supported by LIN-UART only)
2 channels
24 input channels
I
2
C (400 kbps)
A/D converter
16 input channels
10-bit or 8-bit resolution
Conversion time : Min 3
s
include sample time (per one channel)
4 channels
2 channels
Operation clock frequency : fsys/2
1
, fsys/2
3
, fsys/2
5
(fsys
½
Machine clock frequency)
Supports External Event Count function
2 channels
1 channel
16-bit
Reload timer
16-bit
I/O timer
Generates an interrupt signal on overflow
Operation clock freq. : fsys, fsys/2
1
, fsys/2
2
, fsys/2
3
, fsys/2
4
, fsys/2
5
, fsys/2
6
, fsys/2
7
(fsys
½
Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3
I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7
8 channels
16-bit
Output compare
Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare register
A pair of compare registers can be used to generate an output signal.
(Continued)
Document Number: 002-04578 Rev. *A
Page 4 of 64
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