CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
18-Mbit (512K × 36/1M × 18)
Flow-Through SRAM (With ECC)
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM (With ECC)
Features
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Functional Description
The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 are a 3.3 V, 512K × 36 and 1M × 18
synchronous flow through SRAMs, designed to interface with
high speed microprocessors with minimum glue logic. Maximum
access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit
on-chip counter captures the first address in a burst and
increments the address automatically for the rest of the burst
access. All synchronous inputs are gated by registers controlled
by a positive edge triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
chip enable (CE
1
), depth-expansion chip enables (CE
2
and
CE
3
), burst control inputs (ADSC, ADSP, and ADV), write
enables (BW
x
, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
The CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 allows interleaved or linear burst sequences,
selected by the MODE input pin. A HIGH selects an interleaved
burst sequence, while a LOW selects a linear burst sequence.
Burst accesses can be initiated with the processor address
strobe (ADSP) or the cache controller address strobe (ADSC)
inputs. Address advancement is controlled by the address
advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when address strobe processor (ADSP) or address strobe
controller (ADSC) are active. Subsequent burst addresses can
be internally generated as controlled by the advance pin (ADV).
CY7C1381KV33/CY7C1381KVE33/CY7C1383KV33/
CY7C1383KVE33 operates from a +3.3 V core power supply
while all outputs operate with a +2.5 V or +3.3 V supply. All inputs
and outputs are JEDEC-standard and JESD8-5-compatible.
Supports 133 MHz bus operations
512K × 36 and 1M × 18 common I/O
3.3 V core power supply (V
DD
)
2.5 V or 3.3 V I/O supply (V
DDQ
)
Fast clock-to-output time
❐
6.5 ns (133 MHz version)
Provides high performance 2-1-1-1 access rate
User selectable burst counter supporting interleaved or linear
burst sequences
Separate processor and controller address strobes
Synchronous self-timed write
Asynchronous output enable
CY7C1381KV33/CY7C1381KVE33
available
in
JEDEC-standard Pb-free 100-pin TQFP, Pb-free 165-ball
FBGA package. CY7C1383KV33/CY7C1383KVE33 available
in JEDEC-standard Pb-free 100-pin TQFP.
IEEE 1149.1 JTAG-Compatible Boundary Scan
ZZ sleep mode option.
On-chip error correction code (ECC) to reduce soft error rate
(SER)
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Selection Guide
Description
Maximum access time
Maximum operating current
× 18
× 36
133 MHz
6.5
129
149
100 MHz
8.5
114
134
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-97888 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 16, 2018
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Logic Block Diagram – CY7C1381KV33
(512K × 36)
A0, A1, A
ADDRESS
REGISTER
A
[1:0]
MODE
ADV
CLK
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
D
,
DQP
D
BW
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
WRITE REGISTER
DQ
B
,
DQP
B
WRITE REGISTER
WRITE REGISTER
DQ
A
,
DQP
BW
A
BWE
GW
CE1
CE2
CE3
OE
DQ
A
,
DQP
BYTE
WRITE REGISTER
A
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
WRITE REGISTER
DQ
B
,
DQP
B
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
B
BYTE
WRITE REGISTER
ENABLE
REGISTER
INPUT
REGISTERS
SLEEP
Logic Block Diagram – CY7C1381KVE33
(512K × 36)
A0, A1, A
ADDRESS
REGISTER
A
[1:0]
MODE
ADV
CLK
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
D
,
DQP
D
BW
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
A
BW
A
BWE
GW
CE1
CE2
CE3
OE
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BW
B
BYTE
WRITE REGISTER
BW
C
MEMORY
ARRAY
SENSE
AMPS
ECC
DECODER
OUTPUT
BUFFERS
DQs
DQP
A
DQP
B
DQP
C
DQP
D
ENABLE
REGISTER
ECC
ENCODER
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 001-97888 Rev. *F
Page 2 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Logic Block Diagram – CY7C1383KV33
(1M × 18)
A0,A1,A
MODE
ADDRESS
REGISTER
A[1:0]
ADV
BURST Q1
COUNTER AND
Q0
DQ
B
,DQP
B
BW
B
DQ
B
,DQP
B
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ
A
,DQP
A
BW
A
BWE
GW
DQ
A
,DQP
A
WRITE DRIVER
INPUT
REGISTERS
DQs
DQP
A
DQP
B
CE
1
CE
2
CE
3
OE
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1383KVE33
(1M × 18)
Document Number: 001-97888 Rev. *F
Page 3 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................... 9
Burst Sequences ......................................................... 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table ............................... 10
Linear Burst Address Table ....................................... 10
ZZ Mode Electrical Characteristics ............................ 10
Truth Table ...................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
TAP Timing ...................................................................... 17
TAP AC Switching Characteristics ............................... 17
3.3 V TAP AC Test Conditions ....................................... 18
3.3 V TAP AC Output Load Equivalent ......................... 18
2.5 V TAP AC Test Conditions ....................................... 18
2.5 V TAP AC Output Load Equivalent ......................... 18
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
Electrical Characteristics ............................................... 21
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Timing Diagrams ............................................................ 25
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Package Diagrams .......................................................... 30
Acronyms ........................................................................ 32
Document Conventions ................................................. 32
Units of Measure ....................................................... 32
Document History Page ................................................. 33
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC® Solutions ...................................................... 34
Cypress Developer Community ................................. 34
Technical Support ..................................................... 34
Document Number: 001-97888 Rev. *F
Page 4 of 34
CY7C1381KV33/CY7C1381KVE33
CY7C1383KV33/CY7C1383KVE33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3-Chip Enable)
CY7C1381KV33/CY7C1381KVE33 (512K × 36)
CY7C1383KV33/CY7C1383KVE33 (1M × 18)
Document Number: 001-97888 Rev. *F
Page 5 of 34
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