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CY7C1041GN
4-Mbit (256K words × 16 bit) Static RAM
4-Mbit (256K words × 16 bit) Static RAM
Features
■
High speed
❐
t
AA
= 10 ns / 15 ns
Low active and standby currents
❐
Active current: I
CC
= 38-mA typical
❐
Standby current: I
SB2
= 6-mA typical
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
1.0-V data retention
TTL-compatible inputs and outputs
Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA
packages
■
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O
0
through I/O
15
and address on A
0
through A
17
pins. The Byte High
Enable (BHE) and Byte Low Enable (BLE) inputs control write
operations to the upper and lower bytes of the specified memory
location. BHE controls I/O
8
through I/O
15
and BLE controls I/O
0
through I/O
7
.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O
0
through I/O
15
). Byte accesses can be performed by
asserting the required byte enable signal (BHE or BLE) to read
either the upper byte or the lower byte of data from the specified
address location.
All I/Os (I/O
0
through I/O
15
) are placed in a high-impedance state
during the following events:
■
■
■
■
■
■
Functional Description
CY7C1041GN is high-performance CMOS fast static RAM
Organized as 256K words by 16-bits.
The device is deselected (CE HIGH)
The control signals (OE, BLE, BHE) are de-asserted
The logic block diagram is on page 2.
Product Portfolio
Product
Range
V
CC
Range (V)
Speed
(ns)
10/15
CY7C1041GN18
CY7C1041GN30
CY7C1041GN
Industrial
1.65 V–2.2 V
2.2 V–3.6 V
4.5 V–5.5 V
15
10
10
Power Dissipation
Operating I
CC
, (mA)
f = f
max
Typ
[1]
–
38
38
Max
40
45
45
6
8
Standby, I
SB2
(mA)
Typ
[1]
Max
Notes
1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at V
CC
= 1.8 V (for a V
CC
range of 1.65 V–2.2 V),
V
CC
= 3 V (for a V
CC
range of 2.2 V–3.6 V), and V
CC
= 5 V (for a V
CC
range of 4.5 V–5.5 V), T
A
= 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-95413 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 9, 2016
CY7C1041GN
Logic Block Diagram – CY7C1041GN
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
SENSE
AMPLIFIERS
MEMORY
ARRAY
I/O
0
‐I/O
7
I/O
8
‐I/O
15
COLUMN DECODER
A10
A11
A12
A13
A14
A15
A16
A17
BHE
WE
OE
BLE
CE
1
Document Number: 001-95413 Rev. *D
Page 2 of 18
CY7C1041GN
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
AC Switching Characteristics ......................................... 8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Document Number: 001-95413 Rev. *D
Page 3 of 18
CY7C1041GN
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Package/Grade ID: BVXI
[2, 3]
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Package/Grade ID: BVJXI
[2]
1
BLE
I/O
0
I/O
1
VSS
VCC
I/O
6
I/O
7
NC
2
OE
BHE
I/O
2
I/O
3
I/O
4
I/O
5
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
10
I/O
11
I/O
12
I/O
13
WE
A
11
6
NC
I/O
8
I/O
9
VCC
VSS
I/O
14
I/O
15
NC
1
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
VCC
VSS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
BLE
I/O
8
I/O
9
VSS
VCC
I/O
14
I/O
15
NC
A
B
C
D
E
F
G
H
Figure 3. 44-pin TSOP II / 44-pin SOJ pinout
[2]
A0
A1
A2
A3
A4
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/WE
A5
A6
A7
A8
A9
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
44- pin TSOP II
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
A17
A16
A15
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Notes
2. NC pins are not connected internally to the die.
3. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O
[7:0]
and I/O
[15:8]
balls are swapped.
Document Number: 001-95413 Rev. *D
Page 4 of 18
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