SDC-14570/75 SERIES
14- AND 16-BIT TRACKING S/D
CONVERTERS
FEATURES
DESCRIPTION
The SDC-14570/75 Series are small
low cost synchro- or resolver-to-digital
converters based upon a single chip
monolithic. A completely self-con-
tained 14- or 16-bit synchro converter
is housed in the SDC-14570/75
Series small 1.0" x 0.8" package. The
SDC-14570 is fixed at 14 bits, the
SDC-14575 is pin-programmable 14
or 16 bits.
The velocity output (VEL) from the
SDC-14570/75 Series, which can
be used to replace a tachometer, is
a 4 V signal referenced to ground
with a linearity of 1% of output volt-
age.
SDC-14570/75 Series converters
are available with operating temper-
ature ranges of 0°C to +70°C and -
55°C to +125°C, and MIL-PRF-
38534 processing is available.
•
Fixed 14- or 14/16-Bit Resolution
•
BIT for ERROR or LOS
•
No 180° Hangup
•
Small Size 1.0" X 0.8" Package
•
Velocity Output Eliminates
Tachometer
APPLICATIONS
With its low cost, small size, high
accuracy, and versatile performance,
the SDC-14570/75 Series converters
are ideal for use in modern, high-per-
formance military and industrial posi-
tion control systems. Typical applica-
tions include radar antenna position-
ing, navigation and fire control sys-
tems, motor control, and robotics.
•
High Reliability Single Chip
Monolithic
•
-55°C to +125°C Operating
Temperature Range
•
MIL-PRF-38534 Processing
Available
+REF
-REF
R
BIT
REFERENCE CONDITIONER
LOS
BIT
DETECTOR
ERROR
C
I
S1
S2
S3
S4
HYSTERESIS
INTEGRATOR
E
14/16-BIT
UP/DOWN
COUNTER
INPUT OPTION
CONTROL
TRANSFORMER
R
I
GAIN
DEMODULATOR
VEL
VCO & TIMING
DATA LATCH
8
EM DATA
EL
INH
A
CB
FIGURE 1. SDC-14570/75 BLOCK DIAGRAM
©
1991, 1999 Data Device Corporation
TABLE 1. SDC-14570/75 SPECIFICATIONS
These specs apply over the rated power supply, temperature, and refer-
ence frequency ranges; 10% signal amplitude variation, and 10% har-
monic distortion.
PARAMETER
UNIT
VALUE
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
Type
Voltage Range
Frequency
Input Impedance
single ended
differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
90 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
2V Direct Input (L-L)
Voltage Range
Max Voltage No Damage
Input Impedance
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Bits
Min
LSB
LSB
14
4 + 1 LSB
16
2 + 1 LSB
1 max
TABLE 1. SDC 14570/75 SPECIFICATIONS (CONTINUED)
PARAMETER
DIGITAL INPUT/OUTPUT
OUTPUTS
(continued)
Built-In-Test (BIT)
UNIT
VALUE
Drive Capability
1 max
(+REF, -REF )
differential
2 & 11.8 V UNITS
90 V unit
Vrms 2-35
10-130
Hz 360-5000
see note
Ohm 60k
Ohm 120k
Vpeak 50,
100 transient
270k min
540k min
200,
300 transient
DYNAMIC CHARACTERISTICS
Input Frequency
Bandwidth(Closed Loop)
Ka
A1
A2
A
B
Resolution
Tracking Rate
typical
minimum
Acceleration (1 LSB lag)
Settling Time (179° step max)
VELOCITY
CHARACTERISTICS
Polarity
Voltage Range(Full Scale)
Scale Factor
Scale Factor TC
Reversal Error
Linearity
Zero Offset
Zero Offset TC
Load
Noise
DC ERROR (E)
Ohm 123k
Ohm 80k
V
180 max
Logic 0 = BIT condition.
± 100 LSBs of error with a
filter of 500 µs or LOS.
TTL
50 pf +
Logic 0; 1 TTL load, 1.6 mA
at 0.4 V max
Logic 1; 10 TTL loads, -0.4
mA at 2.8 V min
CMOS Logic 0; 100 mV max driving
Logic 1; +5 V supply minus
100 mV min driving
Device Type
60 Hz
4000 Hz
47-5k
360-5k
Hz
15
103
Hz
830
53k
2
1/s
0.17
1.33
1/s
5k
40k
1/s
29
230
1/s
14.5
115
1/s
14
16
14
16
bits
rps
rps
deg/s
2
msec
1.25
1
18
1100
0.31
0.25
4.5
2500
10
8
1160
140
2.5
2
290
320
Ohm 52k
Ohm 34k
V
30 max
Ohm 140k
Ohm 70k
V
30 max
Vrms 2 nom, 2.3 max
V
25 cont, 100 pk transient
Ohm 20 M//10 pF min
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading =10 µA max P.U. current
source to +5 V //5 pF max.
CMOS transient protected
SDC-14575 Series Only
30k pull-down to GND.
Open = 14 bits; +5 V = 16 bits
Logic 0 inhibits; Data
stable within 0.5 µs
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance
Data High Z within 100 ns
bits
8 parallel lines; 2 bytes natural
binary angle, positive logic
0.3 - 1.0 positive pulse.
Data valid 500 ns max after
leading edge
Positive for increasing angle
±V
4.5 typ,4 min
±%
10 typ
20 max
ppm/°C 100 typ 200 max
±%
1 typ
2 max
±%
0.5 typ 1 max
mV
5 typ
10 max
µV/°C 15 typ
30 max
kOhm
20 max
(Vp/V)% 1 typ
2 max
V
-1.25 per +1 LSB error fil-
tered (± 3 LSB range)
+5
-5
5
10
+7
-7
12 typ, 17 max
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current
TEMPERATURE RANGE
Operating
-3XX
-1XX
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
V
±%
V
mA
Resolution Control (A)
Inhibit (lNH)(common)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 14(16) (EL)
°C
°C
°C
0 to +70
-55 to +125
-65 to +150
Outputs
Parallel Data (1-16)
in
(mm)
oz
0.98 x 0.78 x 0.2
(24.9 x 19.8 x 5.1)
0.66
Note: 47 - 5k for 90 V, 60 Hz; 360 - 5k for 90 V, 400 Hz
Converter Busy (CB)
µs
2
THEORY OF OPERATION
The SDC-14570/75 Series of converters are based upon a sin-
gle chip CMOS custom monolithic. They are implemented using
the latest IC technology which merges precision analog circuitry
with digital logic to form a complete high performance tracking
resolver to digital converter.
FIGURE 1 is the Functional Block Diagram of SDC-14570/75
Series. The SDC-14570 Series is fixed at 14 bits. The SDC-
14575 is pin programmable for 14- or 16-bit operation using res-
olution control line “A.” A logic 0 (open line) will select 14 bits; a
logic 1 will select 16-bit operation. The converter operates with
±5 V dc power supplies. Analog signals are referenced to analog
ground, which is at ground potential. The converter is made up of
three main sections; an input front-end, a converter, and a digi-
tal interface. The converter front-end differs for synchro, resolver
and direct inputs. An electronic Scott-T is used for synchro
inputs, a resolver conditioner for resolver inputs and a sine and
cosine voltage follower for direct inputs. These amplifiers feed
the high accuracy Control Transformer (CT). Its other input is the
14-bit digital angle
φ.
Its output is an analog error angle, or dif-
ference angle, between the two inputs. The CT performs the
ratiometric trigonometric computation of SINθCOSφ - COSθSINφ
= SIN(θ-φ) using amplifiers, switches, logic and capacitors in pre-
cision ratios.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters ratioed capacitors
are used in the CT, instead of the more conventional precision
ratioed resistors. Capacitors used as computing elements with
op-amps need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate to eliminate this
drifting and at the same time to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The dc error is inte-
grated yielding a velocity voltage which in turn drives a voltage
controlled oscillator (VCO). This VCO is an incremental integra-
tor (constant voltage input to position rate output) which togeth-
er with the velocity integrator forms a type II servo feedback loop.
A lead in the frequency response is introduced to stabilize the
loop and another lag at higher frequency is introduced to reduce
the gain and ripple at the carrier frequency and above.
- Error Gradient = 0.011 volts per LSB (CT+Error Amp+Demod)
- Integrator gain =
- VCO Gain =
1 volts per second per volt
R
i
C
i
1
LSBs per second per volt
1.25 R
v
C
v
GENERAL SETUP CONSIDERATIONS
The following recommendations should be considered when
connecting the SDC-14570 Series converters:
1) Power supplies are ±5 V dc. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
2) Direct inputs are referenced to Analog GND.
3) Digital Ground should be connected to Analog Ground as
close to the package as possible.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds maximum after the
application of the low-going inhibit pulse.
Output angle data is enabled onto the tri-state data bus in six
bytes. The Enable MSBs (EM) is used for the most significant 8
bits and Enable LSBs (EL) is used for the least significant bits. As
shown in FIGURE 4, output data is valid 150 nanoseconds max-
imum after the application of a low-going enable pulse. The tri-
state data bus returns to the high impedance state 100 nanosec-
onds maximum after the rising edge of the enable signal.
2
-1
/
db
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its Functional Block Diagram and its Bode Plots (open and
closed loop); These are shown in FIGUREs 1 and 2.
The open loop transfer function is as follows:
GAIN = 4
OPEN LOOP
t
oc
(CRITICALLY DAMPED)
2A
ω
(rad/sec)
10B
- GAIN = 0.4
f
3db
= BW =
2 A (Hz)
π
B
A
(B=A/2)
-6
db
/oc
t
Open Loop Transfer Function =
( )
S
(
S +1
10B
)
A
2
2
S +1
B
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
where A is the gain coefficient
and B is the frequency of lead compensation
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
FIGURE 2. BODE PLOTS
3
INHIBIT
PIN 1 DENOTED BY
CONTRASTING
COLORED BEAD
0.98 (MAX)
(24.89)
0.700
(17.78)
0.200 (MAX)
(5.08)
0.210 ±0.010
(5.33 ±0.25)
DATA
;;;;;;
500 ns MAX
DATA
VALID
1
26
8
FIGURE 3. INHIBIT TIMING
0.78 (MAX) 0.600
(19.81)
(15.24)
BOTTOM VIEW
21
14
0.018 ±0.002 DIA. PIN
(0.46 ±0.051)
(26 REQUIRED)
SIDE VIEW
ENABLE
DATA
HIGH Z
FIGURE 4. ENABLE TIMING
; ;
150 ns MAX
DATA
VALID
0.100 (TYP)
(2.54)
PIN NUMBERS ARE
FOR REFERENCE ONLY
100 ns MAX
HIGH Z
FIGURE 5. SDC-14570/75 MECHANICAL OUTLINE
BIT, BUILT-IN-TEST
This output is a logic line that will flag an internal fault condition
or LOS (Loss-Of-Signal). The internal fault detector monitors the
internal error and, when it exceeds ±100 LSBs, will set the line
to a logic 0; this condition will occur during a large-step input and
will reset to a logic 1 after the converter settles out. (The error
voltage is filtered with a 500 µs filter) BIT will set for an overve-
locity condition because the converter loop cannot maintain
input/output sync. BIT will also set if a total LOS (loss of all sig-
nals) occurs.
1 S1(S)
2 S2(S)
3 S3(S)
TABLE 2. PINOUT (26 PIN)*
S1(R) N.C.
26 +REF
(+Reference Input)
S2(R) +COS(D)
25 -REF
(-Reference Input)
S3(R) +SIN(D)
24 Analog Ground
23 EM
22 E
21 VEL
20 INH
19 EL
18 BIT
17 CB
16 Bit 8
15 Bit 7
14 Bit 6
(Enable MSBs)
(DC Error Output)
(Velocity Output)
(Inhibit)
(Enable LSBs)
(Built-In-Test)
(Converter Busy)
/Bit 16**
/Bit 15**
/Bit 14
4 N.C.
S4(R) N.C.
5 A (Resolution Control)**
6 Digital Ground
7
8
-5 V (Power Supply)
+5 V (Power Supply)
/Bit 9
/Bit 10
/Bit 11
/Bit 12
/Bit 13
9 Bit 1 (MSB)
10 Bit 2
11 Bit 3
12 Bit 4
13 Bit 5
NO FALSE 180° HANGUP
This feature eliminates the “false 180° reading” during instanta-
neous 180° step changes; this condition most often occurs when
the input is “electronically switched” from a digital-to-synchro
converter. If the “MSB” (or 180° bit) is “toggled” on and off, a con-
verter without the “false 180° hangup” feature may fail to
respond.
The condition is artificial, as a “real” synchro or resolver cannot
change its output 180° instantaneously. The condition is most
often noticed during wraparound verification tests, simulations,
or troubleshooting.
* Note: (S) = Synchro; (R) = Resolver; (D) = 2 V Resolver Direct
** Note: SDC-14575 Series only
4
ORDERING INFORMATION
SDC-1457X - X X X
Accuracy:
2 = 4 + 1 LSB
4 = 2 minutes + 1 LSB (Not available with 14-bit units.)
Reliability Grade:
0 = Standard DDC procedures
1 = Fully Compliant with MIL-PRF-38534*
2 = Screened to MIL-PRF-38534 but without
QCI testing*
3 = Fully Compliant with MIL-PRF-38534 + PIND Testing*
4 = Fully Compliant with MIL-PRF-38534 + Solder Dip*
5 = Fully Compliant with MIL-PRF-38534 + PIND
Testing + Solder Dip*
6 = Screened to MIL-PRF-38534 + PIND Testing but
without QCI Testing*
7 = Screened to MIL-PRF-38534 + Solder Dip but
without QCI Testing*
8 = Screened to MIL-PRF-38534 + PIND Testing +
Solder Dip but without QCI testing*
Operating Temperature Range:
1 = -55 to +125°C
3 = 0 to +70°C
4 = -55 to +125°C + Variables Data
8 = 0 to +70°C + Variables Data
Input Option:
0 = 11.8 V, Synchro, 14 bit, 400 Hz
1 = 11.8 V, Resolver, 14 bit, 400 Hz
2 = 90 V, Synchro, 14 bit, 400 Hz
3 = 2 V, Direct, 14 bit, 400 Hz
4 = 90 V, Synchro, 14 bit, 60 Hz
5 = 11.8 V, Synchro, 14/16 bit, 400 Hz
6 = 11.8 V, Resolver, 14/16 bit, 400 Hz
7 = 90 V, Synchro, 14/16 bit, 400 Hz
8 = 2 V, Direct 14/16 bit, 400 Hz
9 = 90 V, Synchro, 14/16 bit, 60 Hz
These products contain tin-lead solder finish as applicable to solder dip requirements.
Notes:
* MIL-PRF-38534 product grading is designated with the following dash numbers:
Class H is a -11X, 13X, 14X, 15X, 41X, 43X, 44X, 45X
Class G is a -21X, 23X, 24X, 25X, 51X, 53X, 54X, 55X
Class D is a -31X, 33X, 34X, 35X, 81X, 83X, 84X, 85X
STANDARD DDC PROCESSING
FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS
MIL-STD-883
TEST
INSPECTION
SEAL
TEMPERATURE CYCLE
CONSTANT ACCELERATION
BURN-IN
METHOD(S)
2009, 2010, 2017, and 2032
1014
1010
2001
(Note 1)
1015,
1030
(Note 2)
CONDITION(S)
—
A and C
C
3000g
TABLE 1
Notes:
1. For Process Requirement “B”* (refer to ordering information), devices may be non-compliant with MIL-STD-883, Test
Method 1015, Paragraph 3.2. Contact factory for details.
2. When applicable.
5
DSP 与 ARM 处理器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
