AZ100LVEL16VT
ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
•
•
•
•
•
•
•
High Bandwidth for
≥1GHz
Similar Operation as
AZ100LVEL16VR except in
Disabled Condition: Q
HG
is High
Operating Range of 3.0V to 5.5V
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a 3x3 mm or 2x2 mm
MLP Package
S-Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
PACKAGE
MLP 8 (2x2x0.75)
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
MLP 8 (2x2x0.75)
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
MLP 8 (2x2x0.75)
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
MLP 8 (2x2x0.75)
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
MLP 16 (3x3)
MLP 16 (3x3) RoHS
Compliant / Lead (Pb)
Free
1
2
3
4
5
PACKAGE AVAILABILITY
PART NUMBER
AZ100LVEL16VTNA
AZ100LVEL16VTNA+
AZ100LVEL16VTNB
AZ100LVEL16VTNB+
AZ100LVEL16VTNC
AZ100LVEL16VTNC+
AZ100LVEL16VTND
AZ100LVEL16VTND+
AZ100LVEL16VTL
AZ100LVEL16VTL+
MARKING
P9
<Date Code>
P9+
<Date Code>
P8
<Date Code>
P8+
<Date Code>
P2
<Date Code>
P2+
<Date Code>
P3
<Date Code>
P3+
<Date Code>
AZM
16T
<Date Code>
AZM+
16T
<Date Code>
NOTES
1,2,3
1,2
1,2,4
1,2
1,2,5
1,2
1,2
1,2
1,2
1,2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
Parts marked TNA for date codes prior to 4WW (prior to 2004).
Parts marked TNB for date codes prior to 4WW (prior to 2004).
Parts marked TNC for date codes prior to 4WW (prior to 2004).
DESCRIPTION
The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable.
The Q
HG
/Q
HG
outputs have a voltage gain several times greater than the Q/Q outputs.
¯
¯
MLP 16, 3x3 mm Package (VTL)
The AZ100LVEL16VTL and provide a selectable enable input (EN) that allows continuous oscillator operation.
See truth table for the Enable function. If Enable pull-up is desired in the CMOS/TTL mode, an external
≤20
kΩ
resistor connecting EN to V
CC
will override the on-chip pull-down resistor. When disabled, the Q
HG
output is forced
high and the Q
HG
output is forced low. The AZ100LVEL16VTL also provides a V
BB
and 470
Ω
internal bias
¯
resistors from D to V
BB
and D to V
BB
. The V
BB
pin can support 1.5 mA sink/source current. Bypassing V
BB
to
¯
ground with a 0.01
μF
capacitor is recommended.
The outputs Q and Q each have a selectable on-chip pull-down current source. See truth table below for current
¯
source functions. External resistors may also be used to increase pull-down current to a maximum total of 25 mA.
1630 S. STAPLEY DR., SUITE 127
•
MESA, ARIZONA 85204
•
USA
•
(480) 962-5881
•
FAX (480) 890-2541
www.azmicrotek.com
AZ100LVEL16VT
¯
Outputs Q
HG
and Q
HG
each have an optional on-chip pull-down current source of 10 mA. When pad/pin V
EEP
is
left open (NC), the output current sources are disabled and the Q
HG
/Q
HG
operate as standard PECL/ECL. When V
EEP
¯
is connected to V
EE
, the current sources are activated. The Q
HG
/Q
HG
pull-down current can be decreased, by using a
¯
resistor to connect V
EEP
to V
EE
. (See graph on page 5.)
MLP 8, 2x2 mm Package, VTNA, VTNB, VTNC & VTND Versions
All MLP 8, 2x2mm versions of the AZ100LVEL16VT provide an enable input that allows continuous oscillator
operation. VTNA and VTNB utilize an enable (EN) that operates in the PECL/ECL mode. When the EN input is
¯¯
¯¯
LOW, the Q and Q
HG
/Q
HG
outputs follow the data inputs. When EN is HIGH, the Q
HG
output is forced high and the
¯
¯
¯¯
Q
HG
output is forced low. VTNC and VTND utilize an enable (EN) that operates in the CMOS/TTL mode. When the
¯
EN input is HIGH, the Q and Q
HG
/Q
HG
outputs follow the data inputs. When EN is LOW, the Q
HG
output is forced
¯
¯
high and the Q
HG
output is forced low.
¯
For VTNA and VTND, both D and D inputs are brought out and tied to the V
BB
pin through 470
Ω
internal bias
¯
resistors. In VTNB and VTNC, the D input is internally tied directly to the V
BB
pin and the D input is tied to the V
BB
¯
pin through a 470
Ω
internal bias resistor. Bypassing V
BB
to ground with a 0.01
μF
capacitor is recommended.
All MLP 8, 2x2mm versions (VTNA, VTNB, VTNC & VTND) have the Q, Q
HG
, and Q
HG
current sources
¯
disabled, while the Q output operates with a 4 mA current source to V
EE
.
¯
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
ENABLE TRUTH TABLE
MLP 16 (VTL)
EN-SEL
EN
Q/Q Q
HG
¯
NC
PECL Low, V
EE
or NC
Data Data
NC
PECL High or V
CC
Data High
V
EE
*
Data High
CMOS Low or V
EE
V
EE
*
CMOS High or V
CC
Data Data
Data High
V
EE
*
NC, no external pull-up
Data Data
V
EE
*
NC, with
≤20kΩ
to V
CC
*Connections to V
CC
or V
EE
must be less than 1Ω.
PIN DESCRIPTION
PIN
D/D
¯
Q/Q
¯
Q
HG
/Q
HG
¯
V
BB
EN-SEL
EN/EN
¯¯
CS-SEL
V
EEP
V
EE
V
CC
FUNCTION
Data Inputs
Data Outputs
Data Outputs w/High Gain
Reference Voltage Output
Selects Enable Logic
Enable Input
Selects Q and Q Current Source Magnitude
¯
Optional Q
HG
and Q
HG
Current Sources
¯
Negative Supply
Positive Supply
Q
HG
¯
Data
Low
Low
Data
Low
Data
Q
Q
D
D
V
BB
470 ?
470 ?
4mA EA.
CS-SEL
Q
HG
Q
HG
10mA EA.
EN
CMOS / TTL
THRESHOLD
MLP 16 (VTL)
V
EEP
V
EE
EN-SEL
CURRENT SOURCE TRUTH TABLE
MLP 16 (VTL)
CS-SEL
Q
Q
¯
NC
4mA typ.
4mA typ.
V
EE
*
8mA typ.
8mA typ.
V
CC
*
0
4mA typ.
*Connections to V
CC
or V
EE
must be less than 1Ω.
May 2008 * REV - 11
www.azmicrotek.com
2
AZ100LVEL16VT
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
V
CC
V
I
V
EE
V
I
I
OUT
T
A
T
STG
Characteristic
PECL Power Supply (V
EE
= 0V)
PECL Input Voltage
(V
EE
= 0V)
ECL Power Supply
(V
CC
= 0V)
ECL Input Voltage
(V
CC
= 0V)
¯
Output Current Q
HG
/Q
HG
--- Continuous
--- Surge
Q/Q --- Continuous
¯
Output Current
--- Surge
Operating Temperature Range
Storage Temperature Range
Rating
0 to +8.0
0 to +6.0
-8.0 to 0
-6.0 to 0
50
100
25
50
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
mA
°C
°C
100K ECL DC Characteristics
(V
EE
= -3.0V to -5.5V, V
CC
= GND)
Symbol
V
OH
V
OH
V
OL
V
IH
V
IL
V
BB
I
IL
I
IH
I
EE
1.
2.
3.
4.
Characteristic
-40°C
Min
-1045
-1085
-1925
Max
-835
-880
-1555
Min
-995
-1025
-1900
0°C
Max
-835
-880
-1620
Min
-995
-1025
-1900
25°C
Max
-835
-880
-1620
-880
V
CC
-1475
V
EE
+ 800
-1250
150
48
Min
-995
-1025
-1900
-1165
V
EE
+2000
-1810
V
EE
-1390
0.5
85°C
Max
-835
-880
-1620
-880
V
CC
-1475
V
EE
+ 800
-1250
150
54
Unit
mV
mV
mV
mV
mV
mV
μA
μA
mA
Output HIGH Voltage
2
Output HIGH Voltage
4
Output LOW Voltage
2,4
Input HIGH Voltage
-880
-880
-1165
D/D, EN/EN (PECL)
¯
¯¯
-1165
-1165
V
CC
V
CC
V
EE
+2000
EN (CMOS/TTL) V
EE
+2000
V
EE
+2000
Input LOW Voltage
-1475
-1810
-1475
-1810
D/D, EN/EN (PECL)
¯
¯¯
-1810
V
EE
+ 800
V
EE
V
EE
+ 800
V
EE
EN (CMOS/TTL)
V
EE
Reference Voltage
-1390
-1250
-1390
-1250
-1390
Input LOW Current EN
3
0.5
0.5
0.5
Input HIGH Current EN
3
150
150
Power Supply Current
1
48
48
Specified with V
EEP
and CS-SEL open for VTL. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with V
EEP
and CS-SEL connected to V
EE
for VTL only.
Specified with EN-SEL open for VTL only.
¯
Specified with Q
HG
/Q
HG
connected with 50
Ω
to V
CC
–2V for VTNA, VTNB, VTNC & VTND.
100K LVPECL DC Characteristics
(V
EE
= GND, V
CC
= +3.3V)
Symbol
V
OH
V
OH
V
OL
V
IH
V
IL
V
BB
I
IL
I
IH
I
EE
1.
2.
3.
4.
5.
Characteristic
-40°C
Min
2255
2215
1375
Max
2465
2420
1745
Min
2305
2275
1400
0°C
Max
2465
2420
1655
Min
2305
2275
1480
25°C
Max
2465
2420
1680
2420
V
CC
1825
800
2050
150
48
Min
2305
2275
1400
2135
2000
1490
GND
1910
0.5
85°C
Max
2465
2420
1680
2420
V
CC
1825
800
2050
150
54
Unit
mV
mV
mV
mV
mV
mV
μA
μA
mA
Output HIGH Voltage
1,3
Output HIGH Voltage
1,5
Output LOW Voltage
1,3,5
Input HIGH Voltage
2135
2420
2135
2420
2135
D/D, EN/EN (PECL)
1
¯
¯¯
EN (CMOS/TTL)
2000
V
CC
2000
V
CC
2000
Input LOW Voltage
1490
1825
1490
1825
1490
D/D, EN/EN (PECL)
1
¯
¯¯
EN (CMOS/TTL)
GND
800
GND
800
GND
Reference Voltage
1
1910
2050
1910
2050
1910
4
Input LOW Current EN
0.5
0.5
0.5
Input HIGH Current EN
4
150
150
Power Supply Current
2
48
48
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
Specified with V
EEP
and CS-SEL open for VTL. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with V
EEP
and CS-SEL connected to V
EE
for VTL only.
Specified with EN-SEL open for VTL only.
¯
Specified with Q
HG
/Q
HG
connected with 50
Ω
to V
CC
–2V for VTNA, VTNB, VTNC & VTND.
May 2008 * REV - 11
www.azmicrotek.com
3
AZ100LVEL16VT
100K PECL DC Characteristics
(V
EE
= GND, V
CC
= +5.0V)
Symbol
V
OH
V
OH
V
OL
V
IH
V
IL
V
BB
I
IL
I
IH
I
EE
1.
2.
3.
4.
5.
Characteristic
-40°C
Min
3955
3915
3075
Max
4165
4120
3445
Min
4005
3975
3100
0°C
Max
4165
4120
3338
Min
4005
3975
3100
25°C
Max
4165
4120
3338
4120
V
CC
3525
800
3750
150
48
Min
4005
3975
3100
3835
2000
3190
GND
3610
0.5
85°C
Max
4165
4120
3338
4120
V
CC
3525
800
3750
150
54
Unit
mV
mV
mV
mV
mV
mV
μA
μA
mA
Output HIGH Voltage
1,3
Output HIGH Voltage
1,5
Output LOW Voltage
1,3,5
Input HIGH Voltage
3835
4120
3835
4120
3835
D/D, EN/EN (PECL)
1
¯
¯¯
EN (CMOS/TTL)
2000
V
CC
2000
V
CC
2000
Input LOW Voltage
3190
3525
3190
3525
3190
D/D, EN/EN (PECL)
1
¯
¯¯
EN (CMOS/TTL)
GND
800
GND
800
GND
Reference Voltage
1
3610
3750
3610
3750
3610
Input LOW Current EN
4
0.5
0.5
0.5
4
Input HIGH Current EN
150
150
Power Supply Current
2
48
48
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
Specified with V
EEP
and CS-SEL open for VTL. Subtract 4mA for VTNA, VTNB, VTNC & VTND.
Specified with V
EEP
and CS-SEL connected to V
EE
for VTL only.
Specified with EN-SEL open for VTL only.
¯
Specified with Q
HG
/Q
HG
connected with 50
Ω
to V
CC
–2V for VTNA, VTNB, VTNC & VTND.
AC Characteristics
(V
EE
= -3.0V to -5.5V; V
CC
= GND or V
EE
= GND; V
CC
= +3.0V to +5.5V)
Symbol
t
PLH
/ t
PHL
Characteristic
Min
-40°C
Typ
Max
Min
0°C
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
ps
ps
mV
ps
Propagation Delay
400
400
400
430
(SE)
D to Q/Q Outputs
1
¯
¯
550
550
550
630
D to Q
HG
/Q
HG
Outputs
1
(SE)
2
t
SKEW
Duty Cycle Skew
(SE)
5
20
5
20
5
20
5
20
80
80
80
80
Minimum Input Swing
3
DIFF
V
PP
SE
160
160
160
160
1
Output Rise/Fall Times
100
260
100
260
100
260
100
260
t
r
/ t
f
(20% - 80%)
1.
For VTL, output specified with V
EEP
and CS-SEL connected to V
EE
with an AC coupled 50Ω load. For VTNA, VTNB, VTNC & VTND, AC
¯
coupled 50Ω on Q to V
CC
–2V and DC coupled 50Ω to V
CC
–2V on Q
HG
/Q
HG.
¯
2.
Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device.
3.
V
PP
is the minimum peak-to-peak input swing for which AC parameters guaranteed. The device has a voltage gain of
≈
20 to Q/Q outputs and a
¯
¯
voltage gain of
≈
100 to Q
HG
/Q
HG
outputs.
D
EN
EN
(VTL, VTX)
;
EN
(VTNA, VTNB)
(PECL)
(CMOS)
(VTL, VTX, VTNC, VTND)
Q
Q
Q
HG
Q
HG
TIMING DIAGRAM
May 2008 * REV - 11
www.azmicrotek.com
4
AZ100LVEL16VT
AZ100LVEL16VTL
MLP 16
3x3 mm
Q
16
NC
D
D
V
BB
1
2
3
4
5
EN
6
NC
7
V
EE
8
V
EEP
Q
15
NC
14
V
CC
13
12 CS-SEL
11
Q
HG
10 Q
HG
9
EN-SEL
TOP VIEW
Bottom Center Pad may be left open or tied to V
EE
ADJUSTABLE HIGH GAIN OUTPUT CURRENT
12
HIGH GAIN OUTPUT CURRENTS (mA)
10
8
6
4
2
0
0
20
40
60
80
100
120
140
160
180
200
V
EEP
TO V
EE
RESISTOR VALUE (OHMS)
May 2008 * REV - 11
www.azmicrotek.com
5
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