AZ100LVEL16VT
ARIZONA MICROTEK, INC.
ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
High Bandwidth for
1GHz
Similar Operation as
AZ100LVEL16VR except in
Disabled Condition: Q
HG
is High
-147 dBc/Hz Typical Noise Floor in
Oscillator Applications
Operating Range of 3.0V to 5.5V
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
S-Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
>2 kV HBM ESD Protection
Additional ESD Data Available on
Arizona Microtek Website
PACKAGE
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
MLP 8 (2x2x0.75)
RoHS Compliant /
Lead (Pb) Free
1
2
PACKAGE AVAILABILITY
PART NUMBER
AZ100LVEL16VTNA+
MARKING
P9+
<Date Code>
P8+
<Date Code>
NOTES
1,2
AZ100LVEL16VTNB+
1,2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week.
DESCRIPTION
The AZ100LVEL16VT is a specialized oscillator gain stage with high gain output buffer including an enable.
¯
¯
¯¯
¯
The Q
HG
/Q
HG
outputs have a voltage gain several times greater than the Q output. When the EN input is LOW, the Q
¯
¯¯
¯
and Q
HG
/Q
HG
outputs follow the data inputs. When EN is HIGH, the Q
HG
output is forced high and the Q
HG
output is
forced low.
For the VTNA, both D and D inputs are brought out and tied to the V
BB
pin through 470 internal bias
¯
resistors. In the VTNB, the D input is internally tied directly to the V
BB
pin and the D input is tied to the V
BB
pin
¯
through a 470 internal bias resistor. Bypassing V
BB
to ground with a 0.01
F
capacitor is recommended.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127
MESA, ARIZONA 85204
USA
(480) 962-5881
FAX (623) 505-2414
www.azmicrotek.com
AZ100LVEL16VT
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
V
CC
V
D/D
¯
V
EN
V
EE
V
D/D
¯
V
EN
I
OUT
I
HGOUT
T
A
T
STG
Characteristic
PECL Power Supply
(V
EE
= 0V)
PECL D/D Input Voltage
¯
(V
EE
= 0V)
PECL EN Input Voltage
(V
EE
= 0V)
ECL Power Supply
(V
CC
= 0V)
ECL D/D Input Voltage
¯
(V
CC
= 0V)
ECL EN Input Voltage
(V
CC
= 0V)
Output Current, Q/Q
¯
— Continuous
— Surge
¯
Output Current, Q
HG
/Q
HG
— Continuous
— Surge
Operating Temperature Range
Storage Temperature Range
Rating
0 to +6.0
0.75
with respect to V
BB
0 to +6.0
-6.0 to 0
0.75
with respect to V
BB
-6.0 to 0
25
50
50
100
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
Vdc
Vdc
Vdc
mA
mA
C
C
ECL DC Characteristics
(V
EE
= -3.0V to -5.5V, V
CC
= GND)
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
I
IH
I
IL
I
EE
1.
Characteristic
-40C
Min
-1045
-1925
Max
-835
-1555
Min
-1025
-1900
-1165
-1900
-1390
0C
Max
-835
-1620
-740
-1475
-1250
150
Min
-1025
-1900
-1165
-1900
-1390
25C
Max
-835
-1620
-740
-1475
-1250
150
Min
-1025
-1900
-1165
-1900
-1390
85C
Max
-835
-1620
-740
-1475
-1250
150
Unit
mV
mV
mV
mV
mV
A
A
54
mA
Output HIGH Voltage
1
Output LOW Voltage
1
Input HIGH Voltage
D/D, EN
¯
-1165
-740
Input LOW Voltage
D/D, EN
¯
-1900
-1475
Reference Voltage
-1390
-1250
Input HIGH Current EN
150
Input LOW Current
EN
0.5
Power Supply Current
1
48
Q
HG
/Q
HG
terminated through 50 resistors to V
CC
- 2V.
¯
0.5
48
0.5
48
0.5
LVPECL DC Characteristics
(V
EE
= GND, V
CC
= +3.3V)
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
I
IH
I
IL
I
EE
1.
2.
Characteristic
-40C
Min
2255
1375
Max
2465
1745
Min
2275
1400
0C
Max
2465
1680
Min
2275
1400
25C
Max
2465
1680
2560
1825
2050
150
Min
2275
1400
2135
1400
1910
85C
Max
2465
1680
2560
1825
2050
150
Unit
mV
mV
mV
mV
mV
A
A
54
mA
Output HIGH Voltage
1,2
Output LOW Voltage
1,2
Input HIGH Voltage
1
2135
2560
2135
2560
2135
D/D, EN
¯
1
Input LOW Voltage
D/D, EN
¯
1400
1825
1400
1825
1400
Reference Voltage
1
1910
2050
1910
2050
1910
Input HIGH Current EN
150
150
Input LOW Current
EN
0.5
0.5
0.5
Power Supply Current
2
48
48
For supply voltages other that 3.3V, use the ECL table values and ADD supply voltage value.
¯
Q
HG
/Q
HG
terminated through 50 resistors to V
CC
- 2V.
0.5
48
April 2011 REV- 16
www.azmicrotek.com
2
AZ100LVEL16VT
PECL DC Characteristics
(V
EE
= GND, V
CC
= +5.0V)
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
I
IH
I
IL
I
EE
1.
2.
Characteristic
-40C
Min
3955
3075
Max
4165
3445
Min
3975
3100
0C
Max
4165
3380
Min
3975
3100
25C
Max
4165
3380
4260
3525
3750
150
Min
3975
3100
3835
3100
3610
85C
Max
4165
3380
4260
3525
3750
150
Unit
mV
mV
mV
mV
mV
A
A
54
mA
Output HIGH Voltage
1,2
Output LOW Voltage
1,2
Input HIGH Voltage
1
D/D, EN
¯
3835
4260
3835
4260
3835
Input LOW Voltage
1
D/D, EN
¯
3100
3525
3100
3525
3100
Reference Voltage
1
3610
3750
3610
3750
3610
Input HIGH Current EN
150
150
Input LOW Current
EN
0.5
0.5
0.5
2
Power Supply Current
48
48
For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
¯
Q
HG
/Q
HG
terminated through 50 resistors to V
CC
- 2V.
0.5
48
AC Characteristics
(V
EE
= -3.0V to -5.5V; V
CC
= GND or V
EE
= GND; V
CC
= +3.0V to +5.5V)
Symbol
t
PLH
/ t
PHL
Characteristic
Min
-40C
Typ
Max
Min
0C
Typ
Max
Min
25C
Typ
Max
Min
85C
Typ
Max
Unit
ps
ps
mV
ps
Propagation Delay
350
350
350
350
D to Q Output
1
¯
450
450
450
450
D to Q
HG
/Q
HG
Outputs
2
(SE)
¯
3
t
SKEW
Duty Cycle Skew
(SE)
5
20
5
20
5
20
5
20
Input Swing
4
1000
1000
80
1000
80
Differential (D/D)
¯
80
1000
80
V
PP
1500
1500
160
1500
160
Single Ended (D, D)
¯
160
1500
160
Output Rise/Fall Times
1,2
t
r
/ t
f
100
240
100
240
100
240
100
240
(20% - 80%)
1.
Q output specified with 50 termination to V
CC
- 2V.
¯
2.
Q
HG
/Q
HG
terminated through 50 resistors to V
CC
- 2V.
¯
3.
Duty cycle skew is the difference between a t
PLH
and t
PHL
propagation delay through a device.
4.
The peak-to-peak input swing is the range for which AC parameters are guaranteed. D and D must remain within the range of ± 750 mV with
¯
respect to V
BB
. The device has a voltage gain of
20 to the Q outputs and a voltage gain of
100 to the Q
HG
/Q
HG
outputs.
¯
¯
April 2011 REV- 16
www.azmicrotek.com
3
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