Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F16G08ABABA, MT29F32G08AFABA, MT29F64G08A[J/K/M]ABA,
MT29F128G08AUABA, MT29F16G08ABCBB, MT29F32G08AECBB,
MT29F64G08A[K/M]CBB, MT29F128G08AUCBB
Features
•
Open NAND Flash Interface (ONFI) 2.1-compliant
1
•
Single-level cell (SLC) technology
•
Organization
–
Page size x8: 4320 bytes (4096 + 224 bytes)
–
Block size: 128 pages (512K +28K bytes)
–
Plane size: 2 planes x 2048 blocks per plane
–
Device size: 16Gb: 4096 blocks;
32Gb: 8192 blocks;
64Gb: 16,384 blocks;
128Gb: 32,768 blocks
•
Synchronous I/O performance
–
Up to synchronous timing mode 4
–
Clock rate: 12ns (DDR)
–
Read/write throughput per pin: 166 MT/s
•
Asynchronous I/O performance
–
Up to asynchronous timing mode 4
–
t
RC/
t
WC: 25ns (MIN)
•
Array performance
–
Read page: 25µs (MAX)
–
Program page: 230µs (TYP)
–
Erase block: 700µs (TYP)
•
Operating Voltage Range
–
V
CC
: 2.7–3.6V
–
V
CCQ
: 1.7–1.95V, 2.7–3.6V
•
Command set: ONFI NAND Flash Protocol
•
Advanced Command Set
–
Program cache
–
Read cache sequential
–
Read cache random
–
One-time programmable (OTP) mode
–
Multi-plane commands
–
Multi-LUN operations
–
Read unique ID
–
Copyback
•
First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 107).
•
RESET (FFh) required as first command after power-
on
•
Operation status byte provides software method for
detecting
–
Operation completion
–
Pass/fail condition
–
Write-protect status
•
Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
•
Copyback operations supported within the plane
from which data is read
•
Quality and reliability
–
Data retention: 10 years
–
Endurance: 100,000 PROGRAM/ERASE cycles
•
Operating temperature:
–
Commercial: 0°C to +70°C
–
Industrial (IT): –40ºC to +85ºC
•
Package
–
52-pad LGA
–
48-pin TSOP
–
100-ball BGA
Note:
1. The ONFI 2.1 specification is available at
www.onfi.org.
PDF: 09005aef838cada2
Rev. E 3/10 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at
www.micron.com.
To compare features and specifications by device type,
visit
www.micron.com/products.
Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 16G 08
Micron Technology
NAND Flash
29F = NAND Flash memory
A
B
A
B
A
WP
ES
:B
Design Revision
B = Second revision
Production Status
Blank = Production
ES = Engineering sample
Density
16G = 16Gb
32G = 32Gb
64G = 64Gb
128G = 128Gb
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Device Width
08 = 8 bits
Level
Bit/Cell
A
1-bit
Speed Grade (synchronous mode only)
-12 = 166 MT/s
Classification
Die # of CE# # of R/B# I/O
B
E
F
J
K
M
U
1
2
2
4
4
4
8
1
2
2
2
2
4
4
1
2
2
2
2
4
4
Common
Separate
Common
Common
Separate
Separate
Separate
Package Code
C5 = 52-pad VLGA 14mm x 18mm x 1.0mm
1
H1 = 100-ball VBGA 12mm x 18mm x 1.0mm
1
H2 = 100-ball TBGA 12mm x 18mm x 1.2mm
1
H3 = 100-ball LBGA 12mm x 18mm x 1.4mm
1
WP = 48-pin TSOP
1
(CPL)
Interface
A = Async only
B = Sync/Async
Generation Feature Set
Operating Voltage Range
B = Second set of device features
A = V
CC
: 3.3V (2.7–3.6V), V
CCQ
: 3.3V (2.7–3.6V)
C = V
CC
: 3.3V (2.7–3.6V), V
CCQ
: 1.8V (1.7–1.95V)
Note:
1. Pb-free package.
PDF: 09005aef838cada2
Rev. E 3/10 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ...................................................................................................................................... 14
Architecture ................................................................................................................................................... 19
Device and Array Organization ....................................................................................................................... 20
Bus Operation – Asynchronous Interface ........................................................................................................ 28
Asynchronous Enable/Standby ................................................................................................................... 28
Asynchronous Bus Idle ............................................................................................................................... 28
Asynchronous Commands .......................................................................................................................... 29
Asynchronous Addresses ............................................................................................................................ 30
Asynchronous Data Input ........................................................................................................................... 31
Asynchronous Data Output ........................................................................................................................ 32
Write Protect .............................................................................................................................................. 33
Ready/Busy# .............................................................................................................................................. 33
Bus Operation – Synchronous Interface ........................................................................................................... 38
Synchronous Enable/Standby ..................................................................................................................... 39
Synchronous Bus Idle/Driving .................................................................................................................... 39
Synchronous Commands ........................................................................................................................... 40
Synchronous Addresses .............................................................................................................................. 41
Synchronous DDR Data Input ..................................................................................................................... 42
Synchronous DDR Data Output .................................................................................................................. 43
Write Protect .............................................................................................................................................. 45
Ready/Busy# .............................................................................................................................................. 45
Device Initialization ....................................................................................................................................... 46
Activating Interfaces ....................................................................................................................................... 47
Activating the Asynchronous Interface ........................................................................................................ 47
Activating the Synchronous Interface .......................................................................................................... 47
Command Definitions .................................................................................................................................... 49
Reset Operations ............................................................................................................................................ 51
RESET (FFh) ............................................................................................................................................... 51
SYNCHRONOUS RESET (FCh) .................................................................................................................... 52
Identification Operations ................................................................................................................................ 53
READ ID (90h) ............................................................................................................................................ 53
READ ID Parameter Tables ............................................................................................................................. 54
Configuration Operations ............................................................................................................................... 55
SET FEATURES (EFh) ................................................................................................................................. 55
GET FEATURES (EEh) ................................................................................................................................. 56
READ PARAMETER PAGE (ECh) ...................................................................................................................... 60
Parameter Page Data Structure Tables ............................................................................................................. 61
READ UNIQUE ID (EDh) ................................................................................................................................ 70
Status Operations ........................................................................................................................................... 71
READ STATUS (70h) ................................................................................................................................... 72
READ STATUS ENHANCED (78h) ............................................................................................................... 73
Column Address Operations ........................................................................................................................... 74
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 74
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 75
CHANGE WRITE COLUMN (85h) ................................................................................................................ 76
CHANGE ROW ADDRESS (85h) ................................................................................................................... 77
Read Operations ............................................................................................................................................. 79
PDF: 09005aef838cada2
Rev. E 3/10 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
READ MODE (00h) ..................................................................................................................................... 81
READ PAGE (00h-30h) ................................................................................................................................ 82
READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 83
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 84
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 86
READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 87
Program Operations ....................................................................................................................................... 89
PROGRAM PAGE (80h-10h) ........................................................................................................................ 89
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 91
PROGRAM PAGE MULTI-PLANE 80h-11h ................................................................................................... 93
Erase Operations ............................................................................................................................................ 95
ERASE BLOCK (60h-D0h) ............................................................................................................................ 95
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 96
Copyback Operations ..................................................................................................................................... 97
COPYBACK READ (00h-35h) ....................................................................................................................... 98
COPYBACK PROGRAM (85h–10h) ............................................................................................................... 99
COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 99
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 100
One-Time Programmable (OTP) Operations ................................................................................................... 101
PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 102
PROTECT OTP AREA (80h-10h) .................................................................................................................. 103
READ OTP PAGE (00h-30h) ........................................................................................................................ 104
Multi-Plane Operations ................................................................................................................................. 105
Multi-Plane Addressing ............................................................................................................................. 105
Interleaved Die (Multi-LUN) Operations ........................................................................................................ 106
Error Management ........................................................................................................................................ 107
Output Drive Impedance ............................................................................................................................... 108
AC Overshoot/Undershoot Specifications ...................................................................................................... 111
Synchronous Input Slew Rate ........................................................................................................................ 112
Output Slew Rate ........................................................................................................................................... 113
Electrical Specifications ................................................................................................................................. 114
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 116
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) .................................. 117
Electrical Specifications – DC Characteristics and Operating Conditions (V
CCQ
) ............................................... 117
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 118
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 120
Electrical Specifications – Array Characteristics .............................................................................................. 123
Asynchronous Interface Timing Diagrams ...................................................................................................... 124
Synchronous Interface Timing Diagrams ........................................................................................................ 135
Revision History ............................................................................................................................................ 157
Rev. E, Production – 3/10 ........................................................................................................................... 157
Rev. D, Production – 1/10 .......................................................................................................................... 157
Rev. C – 9/09 ............................................................................................................................................. 157
Rev. B – 2/09 ............................................................................................................................................. 157
Rev. A – 1/09 ............................................................................................................................................. 158
PDF: 09005aef838cada2
Rev. E 3/10 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 27
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 28
Table 4: Synchronous Interface Mode Selection ............................................................................................. 38
Table 5: Command Set .................................................................................................................................. 49
Table 6: Read ID Parameters for Address 00h ................................................................................................. 54
Table 7: Read ID Parameters for Address 20h .................................................................................................. 54
Table 8: Feature Address Definitions .............................................................................................................. 55
Table 9: Feature Address 01h: Timing Mode ................................................................................................... 57
Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 57
Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 58
Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 58
Table 13: Parameter Page Data Structure ....................................................................................................... 61
Table 14: Status Register Definition ............................................................................................................... 71
Table 15: OTP Area Details ........................................................................................................................... 102
Table 16: Error Management Details ............................................................................................................. 107
Table 17: Output Drive Strength Test Conditions (V
CCQ
= 1.7–1.95V) .............................................................. 108
Table 18: Output Drive Strength Impedance Values (V
CCQ
= 1.7–1.95V) .......................................................... 108
Table 19: Output Drive Strength Conditions (V
CCQ
= 2.7–3.6V) ....................................................................... 109
Table 20: Output Drive Strength Impedance Values (V
CCQ
= 2.7–3.6V) ............................................................ 109
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 110
Table 22: Overshoot/Undershoot Parameters ................................................................................................ 111
Table 23: Test Conditions for Input Slew Rate ................................................................................................ 112
Table 24: Input Slew Rate (V
CCQ
= 1.7–1.95V) ................................................................................................. 112
Table 25: Test Conditions for Output Slew Rate ............................................................................................. 113
Table 26: Output Slew Rate (V
CCQ
= 1.7–1.95V) .............................................................................................. 113
Table 27: Output Slew Rate (V
CCQ
= 2.7–3.6V) ................................................................................................ 113
Table 28: Absolute Maximum Ratings by Device ............................................................................................ 114
Table 29: Recommended Operating Conditions ............................................................................................ 114
Table 30: Valid Blocks per LUN ..................................................................................................................... 114
Table 31: Capacitance: 100-Ball BGA Package ................................................................................................ 115
Table 32: Capacitance: 48-Pin TSOP Package ................................................................................................ 115
Table 33: Capacitance: 52-Pad LGA Package .................................................................................................. 115
Table 34: Test Conditions ............................................................................................................................. 116
Table 35: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 116
Table 36: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 117
Table 37: DC Characteristics and Operating Conditions (3.3V V
CCQ
) ............................................................... 117
Table 38: DC Characteristics and Operating Conditions (1.8V V
CCQ
) ............................................................... 118
Table 39: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 118
Table 40: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 120
Table 41: Array Characteristics ..................................................................................................................... 123
List of Tables
PDF: 09005aef838cada2
Rev. E 3/10 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2009 Micron Technology, Inc. All rights reserved.
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