®
Preliminary
SP7653
PowerBlox
Blox
FEATURES
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TM
Wide Input Voltage Range, 1.3MHz,
Buck Regulator
SP7653
DFN PACKAGE
7mm x 4mm
P
GND
1
P
GND
2
P
GND
3
GND 4
V
FB
5
COMP 6
UVIN 7
GND 8
SS 9
V
IN
10
V
IN
11
V
IN
12
V
IN
13
Heatsink pad 3
Connect to VIN
Heatsink pad 2
Connect to GND
TOP VIEW
Heatsink Pad 1
Connect to Lx
26 LX
25 LX
24 LX
23 LX
2 2 V
CC
21 GND
20 GND
19 GND
18 BST
17 NC
16 LX
15 LX
14 LX
2.5V to 20V Step Down Achieved Using Dual Input
Output Voltage down to 0.8V
3A Output Capability
Built in Low R
DSON
Power Switches (40 mΩ typical)
Highly Integrated Design, Minimal Components
1.3MHz Fixed Frequency Operation
UVLO Detects Both V
CC
and V
IN
Over Temperature Protection
Short Circuit Protection with Auto-Restart
Wide BW Amp Allows Type II or III Compensation
Programmable Soft Start
Fast Transient Response
High Efficiency: Greater than
95%
Possible
Asynchronous Start-Up into a Pre-Charged Output
Small 7mm x 4mm DFN Package
Now Available in Lead Free Packaging
DESCRIPTION
The SP7653 is a synchronous step-down switching regulator optimized for high efficiency. The part is designed to be
especially attractive for dual supply, 12V to 20V distributed power systems stepped down with 5V used to power the
controller. This lower V
CC
voltage minimizes power dissipation in the part and is used to drive the top switch. The SP7653
is designed to provide a fully integrated buck regulator solution using a fixed 1.3MHz frequency, PWM voltage mode
architecture. Protection features include Under Voltage Lock Out (UVLO), thermal shutdown and output short circuit
protection. The SP7653 is available in the space saving DFN package
.
TYPICAL APPLICATION CIRCUIT
U1
SP7653
1
P GND
P GND
P GND
GND
V FB
COMP
UV IN
GND
SS
V IN
V IN
V IN
V IN
LX
LX
LX
LX
VCC
GND
GND
GND
BST
NC
LX
LX
LX
26
25
24
23
22
21
20
19
18
17
16
15
14
2
3
L1: IHLP2525CZER2R2M01
2.2uH, Irate =8A
DCR=18mOhm
C3
CERAMIC
X5R
C3
47uF
6.3 V
CZ2
1.5nF
C P1
RZ2
38.3k, 1%
4
5
6
7
8
9
RZ3
158,1%
CZ3
820pF
VOUT
3.30V
0-3A
R1
68.1k,1%
3.3pF
CF1
100pF
CSS
22nF
C VCC
2.2uF
GND2
R BST
5.11, 1%
C BST
1uF
D BST
SD101AWS
R2
21.5k,1%
10
11
12
VIN
12V
C1,C5
CERAMIC
X5R
C1
22uF
16V
C5
22uF
16V
13
R3
200k,1%
fs=1.3MHz
1
2
3
U2
SPX5205
VIN
GND
EN
BYP
4
VOUT
5
Notes:
U1 Bottom-Side Layout should have three
Contacts which are isolated from one
another: QT Contact, QB Drain Contact, and
Controller GND Contact.
ALL RESISTORS & CAPACITORS SIZE 0603 UNLESS
OTHERWISE SPECIFIED.
GND
R4
100k,1%
C2
0.1uF
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
1
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation sections
of the specifications below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect reliability.
V
CC
.................................................................................................. 7V
V
IN ...........................................................................................................................................
20V
I
LX ...............................................................................................................................................
5A
Boost ............................................................................................. 27V
Boost-SWN ....................................................................... -0.3V to 7V
SWN ................................................................................... -1V to 20V
GH ....................................................................... -0.3V to Boost+0.3V
GH-SWN ......................................................................................... 7V
All other pins .......................................................... -0.3V to V
CC
+0.3V
Storage Temperature .................................................. -65°C to 150°C
Power Dissipation ...................................... Internally Limited via OTP
ESD Rating .......................................................................... 2kV HBM
Thermal Resistance
ϑ
JC ....................................................................................
5°C/W
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < T
AMB
< 85°C, -40°C< Tj< 125°C, 4.5V < V
CC
< 5.5V, 3V< Vin< 28V, Boost=LX + 5V,
LX = GND = 0Volts, UV
IN
= 3.0V, CV
CC
= 1µF, C
COMP
= 0.1µF, C
SS
= 50nF, Typical measured at V
CC
= 5V.
The
♦
denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
QUIESCENT CURRENT
V
CC
Supply Current (No switching)
V
CC
Supply Current (switching)
BST Supply Current (No switching)
BST Supply Current (switching)
PROTECTION: UVLO
V
CC
UVLO Start Threshold
V
CC
UVLO Hysteresis
UVIN Start Threshold
UVIN Hysteresis
UVIN Input Current
ERROR AMPLIFIER REFERENCE
Error Amplifier Reference
Error Amplifier Reference
Over Line and Temperature
Error Amplifier Transconductance
Error Amplifier Gain
COMP Sink Current
COMP Source Current
V
FB
Input Bias Current
Internal Pole
COMP Clamp
COMP Clamp Temp. Coefficient
MIN.
TYP.
MAX.
UNITS
CONDITIONS
1.5
8
0.2
4.0
3
mA
mA
♦
V
FB
=0.9V
0.4
mA
mA
♦
V
FB
=0.9V
4.00
100
2.3
200
4.25
200
2.5
300
4.5
300
2.65
400
1
V
mV
V
mV
µA
UVIN= 3.0V
♦
0.792
0.788
0.800
0.800
6
60
150
150
50
4
2.5
-2
0.808
0.812
V
V
mA/V
dB
µA
µA
♦
2X Gain Config., Measure
V
FB
; V
CC
=5 V, T=25ºC
No Load
V
FB
=0.9V, COMP= 0.9V
V
FB
=0.7V, COMP= 2.2V
V
FB
= 0.8V
200
nA
MHz
V
mV/ºC
V
FB
=0.7V, TA=25ºC
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
2
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: -40°C < T
AMB
< 85°C, -40°C< Tj< 125°C, 4.5V < V
CC
< 5.5V, 3V< Vin< 28V, Boost=LX + 5V,
LX = GND = 0Volts, UVIN = 3.0V, CV
CC
= 1µF, C
COMP
= 0.1µF, C
SS
= 50nF, Typical measured at V
CC
= 5V.
The
♦
denotes the specifications which apply over the full temperature range, unless otherwise specified.
PARAMETER
MIN.
TYP.
MAX.
UNITS
CONDITIONS
CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH
Ramp Amplitude
RAMP Offset
RAMP offset Temp. Coefficient
GH Minimum Pulse Width
Maximum Controllable Duty Ratio
Maximum Duty Ratio
Internal Oscillator Ratio
TIMERS: SOFTSTART
SS Charge Current:
SS Discharge Current:
1
10
µA
mA
♦
Fault Present, SS = 0.2V
92
100
1. 1
1.3
1.5
0.92
1.1
1.1
-2
90
97
180
1.28
V
V
mV/ºC
ns
%
%
MHz
♦
♦
Maximum Duty Ratio
Measured just before
pulsing begins
Valid for 20 cycles
T
A
= 25ºC, RAMP COMP
until GH starts Switching
PROTECTION: Short Circuit & Thermal
Short Circuit Threshold Voltage
Hiccup Timeout
Number of Allowable Clock Cycles
at 100% Duty Cycle
Minimum GL Pulse After 20 Cycles
Thermal Shutdown Temperature
Thermal Recovery Temperature
Thermal Hysteresis
OUTPUT: POWER STAGE
High Side Switch R
DSON
Synchronous Lowside Switch R
DSON
Maximum Output Current
3
40
40
m
Ω
m
Ω
A
V
CC
= 5V ; I
OUT
= 3A
T
AMB
= 25ºC
V
CC
= 5V ; I
OUT
= 3A
T
AMB
= 25ºC
0.2
0.25
200
20
0.5
145
135
10
0.3
V
ms
Cycles
Cycles
ºC
ºC
ºC
V
FB
= 0.7V
V
FB
= 0.7V
♦
Measured V
REF
(0.8V) -
V
FB
V
FB
= 0.5V
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
© Copyright 2005 Sipex Corporation
3
PIN DESCRIPTION
Pin #
1-3
4,8,19-21
Pin Name
P
GND
GND
Description
Ground connection for the synchronous rectifier
Ground Pin. The control circuitry of the IC and lower power driver are
referenced to this pin. Return separately from other ground traces to the (-)
terminal of C
OUT
.
Feedback Voltage and Short Circuit Detection pin. It is the inverting input
of the Error Amplifier and serves as the output voltage feedback point for
the Buck Converter. The output voltage is sensed and can be adjusted
through an external resistor divider. Whenever V
FB
drops 0.25V below the
positive reference, a short circuit fault is detected and the IC enters hiccup
mode.
Output of the Error Amplifier. It is internally connected to the inverting input
of the PWM comparator. An optimal filter combination is chosen and
connected to this pin and either ground or V
FB
to stabilize the voltage
mode loop.
UVLO input for Vin voltage. Connect a resistor divider between V
IN
and
UV
IN
to set minimum operating voltage.
Soft Start. Connect an external capacitor between SS and GND to set the
soft start rate based on the 10µA source current. The SS pin is held low
via a 1mA (min) current during all fault conditions.
Input connection to the high side N-channel MOSFET. Place a decoupling
capacitor between this pin and P
GND
.
Connect an inductor between this pin and V
OUT
No Connect
5
V
FB
6
COMP
7
UVIN
9
SS
10-13
14-16,23-26
17
V
IN
LX
NC
THEORY OF OPERATION
General Overview
The SP7653 is a fixed frequency, voltage mode,
synchronous PWM regulator optimized for high
efficiency. The part has been designed to be
especially attractive for high input voltages of
2.5V to 20V.
The heart of the SP7653 is a wide bandwidth
transconductance amplifier designed to accom-
modate Type II and Type III compensation
schemes. A precision 0.8V reference, present on
the positive terminal of the error amplifier per-
mits the programming of the output voltage
down to 0.8V via the V
FB
pin. The output of the
error amplifier, COMP, compared to a 1.1V
peak-to-peak ramp is responsible for trailing
edge PWM control. This voltage ramp, and
PWM control logic are governed by the internal
oscillator that accurately sets the PWM fre-
quency to 1.3MHz.
Date: 03/25/05
The SP7653 contains two unique control fea-
tures that are very powerful in distributed appli-
cations. First, asynchronous driver control is
enabled during start up, to prohibit the low side
switch from pulling down the output until the
high side switch has attempted to turn on. Sec-
ond, a 100% duty cycle timeout ensures that the
low side switch is periodically enhanced during
extended periods at 100% duty cycle. This guar-
antees the synchronized refreshing of the Boost
capacitor during very large duty ratios.
The SP7653 also contains a number of valuable
protection features. Programmable V
IN
UVLO
allows the user to set the exact value at which the
conversion voltage can safely begin down con-
version, and an internal V
CC
UVLO which en-
sures that the controller itself has enough volt-
age to properly operate. Other protection fea-
© Copyright 2005 Sipex Corporation
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
4
THEORY OF OPERATION
tures include thermal shutdown and short-cir-
cuit detection. In the event that either a thermal,
short-circuit, or UVLO fault is detected, the
SP7653 is forced into an idle state where the
output drivers are held off for a finite period
before a restart is attempted.
Soft Start
Thermal and Short-Circuit
Protection
Because the SP7653 is designed to drive large
output current, there is a chance that the power
converter will become too hot. Therefore, an
internal thermal shutdown (145°C) has been
included to prevent the IC from malfunctioning
at extreme temperatures.
A short-circuit detection comparator has also
been included in the SP7653 to protect against
an accidental short at the output of the power
converter. This comparator constantly monitors
the positive and negative terminals of the error
amplifier, and if the V
FB
pin falls more than
250mV (typical) below the positive reference, a
short-circuit fault is set. Because the SS pin
overrides the internal 0.8V reference during soft
start, the SP7653 is capable of detecting short-
circuit faults throughout the duration of soft
start as well as in regular operation.
Handling of Faults:
“Soft Start” is achieved when a power converter
ramps up the output voltage while controlling
the magnitude of the input supply source cur-
rent. In a modern step down converter, ramping
up the positive terminal of the error amplifier
controls soft start. As a result, excess source
current can be defined as the current required to
charge the output capacitor:
I
VIN
= C
OUT
* (DV
OUT
/ DT
SOFT-START
)
The SP7653 provides the user with the option to
program the soft start rate by tying a capacitor
from the SS pin to GND. The selection of this
capacitor is based on the 10uA pull up current
present at the SS pin and the 0.8V reference
voltage. Therefore, the excess source can be
redefined as:
IV
IN
= C
OUT
*[ (DV
OUT
*10µA) /(C
SS
* 0.8V)]
Under Voltage Lock Out (UVLO)
The SP7653 contains two separate UVLO com-
parators to monitor the bias (V
CC
) and conver-
sion (V
IN
) voltages independently. The V
CC
UVLO threshold is internally set to 4.25V,
whereas the V
IN
UVLO threshold is program-
mable through the UV
IN
pin. When the voltage
on the UV
IN
pin is greater than 2.5V, the SP7653
is permitted to start up pending the removal of
all other faults. Both the V
CC
and V
IN
UVLO
comparators have been designed with hysteresis
to prevent noise from resetting a fault.
Upon the detection of power (UVLO), thermal,
or short-circuit faults, the SP7653 is forced into
an idle state where the SS and COMP pins are
pulled low and both switches are held off. In the
event of UVLO fault, the SP7653 remains in this
idle state until the UVLO fault is removed.
Upon the detection of a thermal or short-circuit
fault, an internal 200ms timer is activated. In the
event of a short-circuit fault, a re-start is at-
tempted immediately after the 200ms timeout
expires. Whereas, when a thermal fault is de-
tected the 200ms delay continuously recycles
and a re-start cannot be attempted until the
thermal fault is removed and the timer expires.
Error Amplifier and Voltage Loop
The heart of the SP7653 voltage error loop
compensation is a high performance, wide band-
width transconductance amplifier. Because of
the amplifier’s current limited (+/-150µA)
transconductance, there are many ways to com-
pensate the voltage loop or to control the COMP
© Copyright 2005 Sipex Corporation
Date: 03/25/05
SP7653 Wide Input Voltage Range, 1.3MHz, Buck Regulator
5
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