74HC4020-Q100;
74HCT4020-Q100
14-stage binary ripple counter
Rev. 1 — 23 May 2013
Product data sheet
1. General description
The 74HC4020-Q100; 74HCT4020-Q100 are 14-stage binary ripple counters with a clock
input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel
outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of
CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of
the state of CP. Each counter stage is a static toggle flip-flop.. Inputs include clamp
diodes. This enables the use of current limiting resistors to interface inputs to voltages in
excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Input levels:
For 74HC4020-Q100: CMOS level
For 74HCT4020-Q100: TTL level
Complies with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Applications
Frequency dividing circuits
Time delay circuits
Control counters
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC4020D-Q100
74HCT4020D-Q100
74HC4020PW-Q100
74HCT4020PW-Q100
74HC4020BQ-Q100
74HCT4020BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP16
40 C
to +125
C
Name
SO16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16
leads; body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual in-line compatible thermal
SOT763-1
enhanced very thin quad flat package; no leads;
16 terminals; body 2.5
3.5
0.85 mm
5. Functional diagram
Fig 1.
Functional diagram
CTR14
Q0
Q3
Q4
Q5
10
CP
Q6
Q7
Q8
Q9
11
MR
Q10
Q11
Q12
Q13
9
7
5
4
6
13
12
14
15
1
2
3
13
CT
10
11
+
CT = 0
0
9
7
5
4
6
13
12
14
15
1
2
3
001aal202
001aal203
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT4020_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
2 of 18
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
Q
CP
FF
T 1
Q
RD
MR
RD
FF
T 2
Q
FF
T 3
Q
RD
Q
FF
T 4
Q
RD
Q
FF
T 6
Q
RD
Q
Q
Q0
Q3
Q13
001aal204
Fig 4.
Logic diagram
6. Pinning information
6.1 Pinning
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5.
Pin configuration SO16 and TSSOP16
Fig 6.
Pin configuration DHVQFN16
74HC_HCT4020_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
3 of 18
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
6.2 Pin description
Table 2.
Symbol
Q0, Q3 to Q13
GND
CP
MR
V
CC
Pin description
Pin
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3
8
10
11
16
Description
output
ground (0 V)
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
7. Functional description
Table 3.
Input
CP
X
[1]
Function table
Output
MR
L
L
H
Q0, Q3 to Q13
no change
count
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
7.1 Timing diagram
1
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aal207
2
4
8
16
32
64
128
256
512 1024 2048 4096 8192 16384
Fig 7.
Timing diagram
74HC_HCT4020_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
4 of 18
NXP Semiconductors
74HC4020-Q100; 74HCT4020-Q100
14-stage binary ripple counter
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
-
65
Max
+7
20
20
25
50
50
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
[1]
-
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Conditions
74HC4020-Q100
Min
V
CC
V
I
V
O
t/V
supply voltage
input voltage
output voltage
input transition rise and
fall rate
except for
Schmitt trigger inputs
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
T
amb
ambient temperature
-
-
-
40
-
1.67
-
+25
625
139
83
+125
-
-
-
40
-
1.67
-
+25
-
139
-
+125
ns/V
ns/V
ns/V
C
2.0
0
0
Typ
5.0
-
-
Max
6.0
V
CC
V
CC
74HCT4020-Q100
Min
4.5
0
0
Typ
5.0
-
-
Max
5.5
V
CC
V
CC
V
V
V
Unit
Symbol Parameter
74HC_HCT4020_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 23 May 2013
5 of 18
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