CAT34RC02
2-kb I
2
C Serial EEPROM, Serial Presence Detect
FEATURES
I
400 kHz I
2
C bus compatible*
I
1.7 to 5.5 volt operation
I
16-byte page write buffer
I
Hardware write protection for entire memory
I
Permanent and reversible software write
I
Schmitt trigger on SCL and SDA inputs
I
Low power CMOS technology
I
1,000,000 program/erase cycles
I
100 year data retention
I
8-pin TSSOP and TDFN packages
I
Industrial temperature range
protection for lower 128 bytes
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features
a 16-byte page write buffer. The device operates via the
I
2
C bus serial interface and is available in 8-pin TSSOP
and TDFN packages.
PIN CONFIGURATION
TDFN Package (SP2, VP2)
FUNCTIONAL SYMBOL
VCC
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
SCL
TSSOP Package (U, Y, GY)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A2, A1, A0
WP
CAT34RC02
SDA
VSS
PIN FUNCTIONS
Pin Name
A
0
, A
1
, A
2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
1.7 V to 5.5 V Power Supply
Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1052, Rev. O
1
CAT34RC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
............ -2.0 V to V
CC
+ 2.0 V
Voltage on A
0 ..................................................
-2.0 V to +12.0 V
V
CC
with Respect to V
SS ..............................
-2.0 V to +7.0 V
RELIABILITY CHARACTERISTICS
(2)
Symbol
N
END(*)
T
DR(*)
V
ZAP(*)
I
LTH(3)
(*) Page Mode, VCC = 5 V, 25°C
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min
1,000,000
100
4000
100
Units
Program/ Erase Cycles
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, unless otherwise specified.
Symbol
I
CC
I
CC
I
SB(4)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
V
HV
Parameter
Power Supply Current (Read)
Power Supply Current (Write)
Standby Current (V
CC
= 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0 V)
Output Low Voltage (V
CC
= 1.7 V)
RSWP Set/Clear Overdrive
A
0
High Voltage
Test Conditions
f
SCL
= 100 kHz
f
SCL
= 100 kHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
Min
Typ
Max
1
3
1
1
1
Units
mA
mA
µA
µA
µA
V
V
V
V
V
–1
V
CC
x 0.7
I
OL
= 3 mA
I
OL
= 1.5 mA
V
HV
- V
CC
> 4.8 V
7
V
CC
x 0.3
V
CC
+ 1.0
0.4
0.5
10
CAPACITANCE
T
A
= 25°C, f = 400 kHz, V
CC
= 5 V
Symbol
C
I/O(2)
C
IN(2)
Z
WPL
Z
WPH
Test
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
WP Input Impedance
WP Input Impedance
Conditions
V
I/O
= 0 V
V
IN
= 0 V
V
IN
< 0.5 V
V
IN >
V
CC
x 0.7
5
500
Min
Typ
Max
8
6
70
Units
pF
pF
kΩ
kΩ
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin
may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC
voltage on address pin A
0
is +12.0 V.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to V
CC
+ 1.0 V.
(4) Standby Current, I
SB
= 10
µA
max at extended temperature range.
Doc. No. 1052, Rev. O
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT34RC02
A.C. CHARACTERISTICS
V
CC
= 1.7 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.7 V - 5.5 V
Min
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
250
1
300
0.6
100
Max
100
100
3.5
1.3
0.6
1.3
0.6
0.6
0
100
0.3
300
2.5 V - 5.5 V
Min
Max
400
100
0.9
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle time is the time elapsed between the
STOP command (following the write instruction) and the
completion of the internal write cycle. During the internal
write cycle, SDA is released by the Slave and the device
does not acknowledge external commands.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1052, Rev. O
CAT34RC02
FUNCTIONAL DESCRIPTION
The CAT34RC02 supports the I
2
C (2-wire) Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT34RC02
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master alone assigns those roles. A maximum of 8
devices may be connected to the bus as determined by
the device address inputs A
0
, A
1
, and A
2
.
PIN DESCRIPTIONS
SCL:
Serial Clock
The serial clock input pin is used to clock all data
transfers into or out of the device.
SDA:
Serial Data/Address
The bidirectional serial data/address pin is used to
transfer data into and out of the device. This pin is an
open drain output in transmit mode.
A
0
, A
1
, A
2
:
Device Address Inputs
These inputs set the device address. When left floating,
the address pins are internally pulled to ground.
WP:
Write Protect
This input, when grounded or left floating, allows write
operations to the entire memory. When this pin is tied to
V
CC
, the entire memory is write protected.
Figure 1. Bus Timing
tF
tLOW
tHIGH
tLOW
tR
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
SDA OUT
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
Doc. No. 1052, Rev. O
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
CAT34RC02
I
2
C BUS PROTOCOL
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two ‘wires’ are connected to the supply (V
CC
) via pull-up
resistors. Master and Slave devices connect to the bus
via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
(1) Data transfer may be initiated only when the bus is
not busy (see A.C. Characteristics).
(2) During a data transfer, the data line must remain
stable whenever the SCL line is high. An SDA
transition while SCL is high will be interpreted as a
START or STOP condition.
START Condition
The START Condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START condition acts as a ‘wake-up’ call for the
Slave devices. A Slave will not respond to commands
unless the MASTER generates a START condition.
STOP Condition
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP condition starts the internal write cycle, when
following a WRITE command and sends the Slave into
standby mode, when following a READ command.
Device Addressing
The Master initiates a data transfer by creating a START
condition on the bus. The Master then broadcasts an 8-
bit serial Slave address. The four most significant bits of
the Slave address (the ‘preamble’) are fixed to 1010
(Ah), for normal read/write operations and 0110 (6h) for
Software Write Protect (SWP) operations (Fig. 5). The
next three bits, A
2
, A
1
and A
0
, select one of eight possible
Slave devices. The last bit, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9
th
clock cycle. The Slave will aslo
acknowledge the 8-bit byte address and every data byte
presented in WRITE mode. In READ mode the Slave
shifts out eight bits of data, and then ‘releases’ the SDA
line durng the 9
th
clock cycle. If the Master acknowledges
in the 9
th
clock cycle (by pulling down the SDA line), then
the Slave continues transmitting. When data transfer is
complete, the Master responds with a NoACK (it does
not acknowledge the last data byte) and the Slave stops
transmitting and waits for a STOP condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
Normal Read and Write
DEVICE ADDRESS
0
1
1
0
A2
A1
A0
R/W
Programming the Write
Protect Register
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1052, Rev. O
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