Numonyx™ Wireless Flash Memory
(W18 SCSP)
128-Mbit W18 Family with Synchronous PSRAM
Datasheet
Product Features
Device Architecture
— Flash Die Density: 32, 64 or 128-Mbit
— PSRAM Die Density: 16 or 32-Mbit
— x16 Non-Mux or ADMux I/O Interface Option
— Bottom or Top Flash Parameter
Configuration
Device Voltage
— Core: V
CC
= 1.8 V
— I/O: V
CCQ
= 1.8 V
Device Packaging
— Ballout: QUAD+ (88 Balls)
— Area: 8x10 mm
— Height: 1.2 mm
PSRAM Performance
— 70 ns Initial Read Access;
20 ns Asynchronous Page-Mode Read
— Up to 66 MHz with 9 ns Clock-to-Data
Synchronous Burst-Mode Reads and Writes
— Configurable 4-, 8-, 16- and Continuous-
Word Burst-Length Reads and Writes
— Partial-Array Self and Temperature-
Compensated Refresh
— Programmable Output Impedance
Flash Performance
— 60 ns Initial Read Access;
20 ns Asynchronous Page-Mode Read
— Up to 66 MHz with 11 ns Clock-to-Data
Output Synchronous Burst-Mode Read
— Enhanced Factory Programming Modes:
3.1 µs/Word (Typ)
Flash Architecture
— Read-While-Write/Erase
— Asymmetrical blocking structure
— 4-KWord parameter blocks (Top or Bottom)
— 32-KWord main blocks
— 4-Mbit partition size
— 128-bit One-Time Programmable (OTP)
Protection Register
— Zero-latency block locking
— Absolute write protection with block lock
using F-VPP and F-WP#
Flash Software
— Numonyx™ FDI, Numonyx™ PSM, and
Numonyx™ VFM
— Common Flash Interface
— Basic and Extended Flash Command Set
Quality and Reliability
— Extended Temperature –25 °C to +85 °C
— Minimum 100K Flash Block Erase cycles
— 90 nm ETOX ™ IX Flash Technology
— 130 nm ETOX™ VIII Flash Technology
Order Number: 311760-10
November 2007
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal L ines and D isc laim er s
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at
http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007, Numonyx B.V., All Rights Reserved.
Datasheet
2
November 2007
Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Contents
1.0
Introduction
.............................................................................................................. 6
1.1
Nomenclature ..................................................................................................... 6
1.2
Acronyms........................................................................................................... 7
1.3
Conventions ....................................................................................................... 7
Functional Overview
.................................................................................................. 8
2.1
Product Description ............................................................................................. 8
2.2
Device Combinations ........................................................................................... 9
2.3
Device Operation Overview................................................................................. 10
2.3.1 Flash and Synchronous PSRAM Bus Operations........................................... 10
2.3.2 Flash Configuration Operation .................................................................. 11
2.3.3 Flash Memory Map and Partitioning........................................................... 11
Device Package Information
.................................................................................... 12
Ballout and Signal Descriptions
............................................................................... 13
4.1
Device Signal Ballout ......................................................................................... 13
4.2
Signal Descriptions ............................................................................................ 14
Maximum Ratings and Operating Conditions............................................................
16
5.1
Device Absolute Maximum Ratings....................................................................... 16
5.2
Device Operating Conditions ............................................................................... 17
Device Electrical Specifications................................................................................
17
6.1
Flash DC Characteristics ..................................................................................... 17
6.2
Synchronous PSRAM DC Characteristics................................................................ 17
6.3
Device AC Test Conditions .................................................................................. 19
6.3.1 Flash Die Capacitance ............................................................................. 19
6.3.2 Synchronous PSRAM Die Capacitance ........................................................ 19
Device AC Characteristics
........................................................................................ 19
7.1
Flash AC Characteristics ..................................................................................... 19
7.2
PSRAM Asynchronous Read................................................................................. 19
7.3
PSRAM Asynchronous Write ................................................................................ 23
7.4
PSRAM Synchronous Read and Write.................................................................... 26
Device Bus Interface
............................................................................................... 31
8.1
PSRAM Reads ................................................................................................... 31
8.1.1 PSRAM Asynchronous Read...................................................................... 31
8.1.2 PSRAM Asynchronous Page-Mode Read ..................................................... 32
8.1.3 PSRAM Synchronous Burst-Mode Reads..................................................... 32
8.1.4 PSRAM Asynchronous Fetch Control Register Read ...................................... 32
8.2
PSRAM Writes ................................................................................................... 33
8.2.1 PSRAM Asynchronous Write ..................................................................... 33
8.2.2 PSRAM Synchronous Write....................................................................... 33
8.2.3 PSRAM Asynchronous Set Control Register Write ........................................ 34
8.2.4 PSRAM Synchronous Set Control Register Write.......................................... 34
8.3
PSRAM No Operation Command .......................................................................... 34
8.4
PSRAM Deselect ................................................................................................ 35
8.5
PSRAM Deep Power Down................................................................................... 35
8.6
PSRAM WAIT Signal........................................................................................... 35
Device Operations
................................................................................................... 37
9.1
Device Power-Up/Down...................................................................................... 37
9.1.1 Flash Power and Reset Specifications ........................................................ 37
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
November 2007
Order Number: 311760-10
Datasheet
3
128-Mbit W18 Family with Synchronous PSRAM
9.2
9.3
9.4
9.5
9.6
9.7
9.1.2
PSRAM
PSRAM
9.3.1
9.3.2
PSRAM
9.4.1
9.4.2
9.4.3
PSRAM
9.5.1
PSRAM
9.6.1
9.6.2
9.6.3
PSRAM
PSRAM Power-Up Sequence and Initialization .............................................37
Operating Modes .....................................................................................37
Control Registers ....................................................................................38
PSRAM Bus Control Register .....................................................................38
PSRAM Refresh Control Register ...............................................................42
Access to Control Register ........................................................................45
PSRAM Hardware Control Register Access ..................................................45
PSRAM Software Register Access ..............................................................45
Cautionary Note About Software Register Access.........................................46
Self-Refresh Operation.............................................................................47
PSRAM Self-Refresh Operations at Low Frequency .......................................47
Burst Suspend, Interrupt, or Termination ...................................................47
PSRAM Burst Suspend .............................................................................47
PSRAM Burst Interrupt ............................................................................48
PSRAM Burst Termination ........................................................................49
Row Boundary Crossing ...........................................................................49
10.0 Additional Information.............................................................................................50
11.0 Ordering Information
...............................................................................................51
Datasheet
4
November 2007
Order Number: 311760-10
128-Mbit W18 Family with Synchronous PSRAM
Revision History
Date
February 2006
Revision
001
Initial release
•
March 2006
002
•
•
•
•
Corrected flash and PSRAM specification of CLK from 66 MHz to 54 MHz, and flash burst-mode
read timing from 11 ns to 14 ns.
Remove Page-Mode Read details for flash and PSRAM, feature not supported.
Changed tCLK3 Min value in
Section 11, “PSRAM AC Characteristics—Asynchronous Read” on
page 21
from 15 ns to 18 ns to correlate CLK value change.
Updated Ordering Information Table.
Added ADMux I/O interface flash references, making document inclusive of Non-Mux and
ADMux I/O flash interface WQ product family, superseding 64-Mbit WQ Family with
Synchronous PSRAM datasheet #311641.
Updated PSRAM burst-mode improved read timing from 14 ns to 9 ns. Added 16 Mbit PSRAM
AC/DC specifications that was TBD in revision -002.
Update various descriptions of the W18 and PSRAM features, specifications and operations for
clarity.
Made miscellaneous edits and formatting changes.
Added 90 nm device option.
Revised datasheet to show improved CLK from 54 MHz to 66 MHz for Non Mux and AD Mux
products.
Revised datasheet to show improved flash burst mode read timing from 14 ns to 11 ns.
Revised ordering information to add non-muxed line items
Added section for configuring device in asynchronous mode. Revised typos in Ordering
infomation: Changed AD-Mux to Non-Mux. Added LIs PF38F2030W0YTQE and
PF38F2040W0YCQE.
Updated ordering information
Applied Numonyx branding.
Description
May 2006
003
•
•
July 2006
August 2006
November 2006
January 2007
July 2007
August 2007
November 2007
004
005
006
•
•
•
•
007
008
009
10
•
•
•
•
November 2007
Order Number: 311760-10
Datasheet
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
