1GB, 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM RDIMM
Features
DDR3 SDRAM RDIMM
MT9JSF12872PY – 1GB
MT9JSF25672PY – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as per
component data sheet
• 240-pin, registered dual in-line memory module
(RDIMM)
• Fast data transfer rates: PC3-10600, PC3-8500,
or PC3-6400
• 1GB (128 Meg x 72), 2GB (256 Meg x 72)
• V
DD
= V
DD
Q = 1.5V ±0.075V
• V
DDSPD
= +3V to +3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single rank
• Eight internal device banks for concurrent operation
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
via the mode register set
• Adjustable data-output drive strength
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• I
2
C temperature sensor
• Pb-free
• Fly-by topology
• Terminated command, address, and control bus
Figure 1:
240-Pin RDIMM (MO-269 R/C A)
PCB height: 30.0mm (1.18in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Frequency/CAS latency
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.5ns @ CL = 10 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
–
2.5ns @ CL = 5 (DDR3-800)
–
2.5ns @ CL = 6 (DDR3-800)
1
Marking
None
I
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
Table 1:
Speed
Grade
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Industry
Nomenclature
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
Data Rate (MT/s)
CL = 10 CL = 9
–
1333
–
–
–
–
1333
1066
–
–
–
–
CL = 8
1066
800
–
1066
–
–
CL = 7
800
–
1066
800
–
–
CL = 6
–
–
800
–
–
800
CL = 5
–
–
–
–
800
–
t
RCD
t
RP
t
RC
(ns)
13.5
15
13.125
15
12.5
15
(ns)
13.5
15
13.125
15
12.5
15
(ns)
49.5
51
50.625
52.5
50
52.5
PDF: 09005aef829eedac/Source: 09005aef829eede3
JTF9C128_256x72PY.fm - Rev. A 7/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM RDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
Addressing
1GB
8K
16K (A0–A13)
8 (BA0–BA2)
1KB
1Gb (128 Meg x 8)
1K (A0–A9)
1 (S0#)
2GB
8K
32K (A0–A14)
8 (BA0–BA2)
1KB
2Gb (256 Meg x 8)
1K (A0–A9)
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
MT9JSF12872P(I)Y-1G4__
MT9JSF12872P(I)Y-1G3__
MT9JSF12872P(I)Y-1G1__
MT9JSF12872P(I)Y-1G0__
MT9JSF12872P(I)Y-80C__
MT9JSF12872P(I)Y-80B__
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
Table 4:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
Module
Bandwidth
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
MT9JSF25672P(I)Y-1G4__
MT9JSF25672P(I)Y-1G3__
MT9JSF25672P(I)Y-1G1__
MT9JSF25672P(I)Y-1G0__
MT9JSF25672P(I)Y-80C__
MT9JSF25672P(I)Y-80B__
Notes:
Configuration
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
1. Data sheets for the base device parts can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT9JSF12872PY-1G1B1.
PDF: 09005aef829eedac/Source: 09005aef829eede3
JTF9C128_256x72PY.fm - Rev. A 7/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM RDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
240-Pin RDIMM Front
240-Pin RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
REF
DQ
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
TT
V
TT
CKE0
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
A2
V
DD
NC
NC
V
DD
91
92
93
94
95
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SA0
SCL
SA2
V
TT
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
V
SS
DQ4
DQ5
V
SS
DM0/
DQS9
DQS9#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1/
DQS10
DQS10#
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DM2/
DQS11
DQS11#
V
SS
DQ22
DQ23#
V
SS
DQ28
DQ29
151
152
V
SS
DM3/
DQS12
153 DQS12#
154
V
SS
155 DQ30
DQ31
V
SS
CB4
CB5
V
SS
DM8/
DQS17
162 DQS17#
163
V
SS
164
CB6
CB7
V
SS
NC
RESET#
NC
V
DD
A15
A14
V
DD
A12
A9
V
DD
A8
A6
V
DD
A3
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
A1
V
DD
V
DD
CK0
CK0#
V
DD
NC
A0
V
DD
BA1
V
DD
RAS#
S0#
V
DD
ODT0
A13
V
DD
NC
V
SS
DQ36
DQ37
V
SS
DM4/
DQS13
DQS13#
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DM5/
DQS14
213 DQS14#
214
V
SS
215 DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6/
DQS15
222 DQS15#
223
V
SS
224 DQ54
225
226
227
228
229
230
DQ55
V
SS
DQ60
DQ61
V
SS
DM7/
DQS16
231 DQS16#
232
V
SS
233 DQ62
DQ63
V
SS
V
DDSPD
SA1
SDA
V
SS
V
TT
216
217
218
219
220
221
211
212
96
V
DD
V
REF
CA 97
P
AR
_I
N
98
99
V
DD
A10
100
BA0
101
V
DD
WE#
CAS#
V
DD
S1
ODT1
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
156
157
158
159
160
161
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
81
51
V
DD
52
BA2
82
53 E
RR
_O
UT
# 83
54
55
56
57
58
59
60
V
DD
A11
A7
V
DD
A5
A4
V
DD
84
85
86
87
88
89
90
234
235
236
237
238
239
240
PDF: 09005aef829eedac/Source: 09005aef829eede3
JTF9C128_256x72PY.fm - Rev. A 7/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM RDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A0–A15
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands and the column address
and auto precharge bit for READ/WRITE commands to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also used
for BC = 4/BL = 8 identification as “BL on the fly” during CAS commands. The address
inputs also provide the op-code during mode register command set
.
A0–A13 (1GB), A0–
A14 (2GB), and A15 is used as part of the parity calculation.
Bank address inputs:
BA0–BA2 define to which device bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0–BA2 define which mode register, including
MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command. BA0–BA1 are
used as part of the parity calculation.
Clock:
CK0 and CK0# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR3 SDRAM.
Data input mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
On-die termination:
ODT (registered HIGH) enables termination resistance internal to
the DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,
DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Parity input:
Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
An active LOW CMOS input referenced to V
SS
and not referenced to V
REF
CA or
V
REF
DQ. The reset pin input receiver is a CMOS input and is defined as a rail-to-rail signal
with a DC HIGH
≥
0.8 × V
DD
Q and DC LOW
≤
0.2
×
V
DD
Q (1.20V for HIGH and 0.30V for
LOW). RESET# assertion and desertion are asynchronous. System applications will most
likely be unterminated, heavily loaded, and have very slow slew rates. A slow slew rate
receiver design is recommended along with implementing on-chip noise filtering to
prevent false triggering (RESET# assertion minimum pulse width is 100ns).
Serial address inputs:
These pins are used to configure the SPD EEPROM address range.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder. With both inputs HIGH, all outputs of the register(s) are disabled except for CKE
and ODT.
Serial clock for presence-detect and temperature sensor:
SCL is used to synchronize
the communication to and from the EEPROM temperature sensor.
Data input/output:
Bidirectional data bus.
Check bits:
Data used for ECC.
Data strobe:
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only used
when differential data strobe mode is enabled via the LOAD MODE command.
DQS0–DQS8/DQS0#–DQS8# are inputs only when TDQS is disabled on x8 modules.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the SPD EEPROM on the module.
Temperature event:
The optional event pin is used to flag critical module temperatures
when used in conjunction with a temperature senor.
BA0–BA2
Input
CK0, CK0#
Input
CKE0
DM0–DM8
(DQS9–DQS17)
Input
Input
ODT
Input
P
AR
_I
N
RAS#, CAS#,
WE#
RESET#
Input
Input
Input
(LVCMOS)
SA0–SA2
S0#, S1#
Input
Input
SCL
DQ0–DQ63
CB0–CB7
DQS0–DQS8,
DQS0#–DQS8#
Input
I/O
I/O
I/O
SDA
EVENT#
I/O
Output
PDF: 09005aef829eedac/Source: 09005aef829eede3
JTF9C128_256x72PY.fm - Rev. A 7/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC, SR) 240-Pin DDR3 SDRAM RDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
E
RR
_O
UT
V
DD
V
SS
V
TT
V
DDSPD
V
REF
DQ
V
REF
CA
NC
Pin Descriptions (continued)
Type
Output
(open drain)
Supply
Supply
Supply
Supply
Supply
Supply
–
Description
Parity error output:
Parity error found on the command, address, and control bus.
Power supply:
1.5V ±0.075V.
Ground.
Termination voltage:
Used for address, command, and control. V
DD
/2.
Serial EEPROM and temperature sensor power supply:
+3V to +3.6V.
Reference voltage:
DQ, DM. V
DD
/2.
Reference voltage:
Command, address, and control. V
DD
/2.
No connect:
These pins should be left unconnected.
PDF: 09005aef829eedac/Source: 09005aef829eede3
JTF9C128_256x72PY.fm - Rev. A 7/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
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