8, 16 MEG x 64
SDRAM DIMMs
SYNCHRONOUS
DRAM MODULE
FEATURES
• PC66-, PC100- and PC133-compliant
• JEDEC-standard 168-pin, dual in-line memory
module (DIMM)
• Utilizes 100 MHz, 125 MHz and 133 MHz SDRAM
components
• Unbuffered
• 64MB (8 Meg x 64) and 128MB (16 Meg x 64)
• Single +3.3V ±0.3V power supply
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal SDRAM banks for hiding row access/
precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Serial Presence-Detect (SPD)
MT8LSDT864A, MT16LSDT1664A
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Front View)
168-Pin DIMM
64MB, 66 MHz; 64MB, 100 MHz; 128MB
OPTIONS
• Operating Temperature Range
Commercial (-0
o
C to +70
o
C)
Extended (-40
o
C to +85
o
C)
MARKING
G
I
• Frequency/CAS Latency
133 MHz/CL = 2 (7.5, 133MHz SDRAMs)
133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs)
100 MHz/CL = 2 (8ns, 125 MHz SDRAMs)
66 MHz/CL = 2 (10ns, 100 MHz SDRAMs)
-13E
-133
-10E
-662
KEY SDRAM COMPONENT
TIMING PARAMETERS
MODULE SPEED
MARKING GRADE
-13E
-133
-10E
-662
-7E
-75
-8E
-10
CAS
ACCESS
LATENCY
TIME
2
3
2
2
5.4ns
5.4ns
6ns
9ns
SETUP
TIME
1.5ns
1.5ns
2ns
3ns
HOLD
TIME
0.8ns
0.8ns
1ns
1ns
PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
V
SS
43
V
SS
85
V
SS
2
DQ0
44
DNU
86
DQ32
3
DQ1
45
S2#
87
DQ33
4
DQ2
46
DQMB2
88
DQ34
5
DQ3
47
DQMB3
89
DQ35
6
V
DD
48
DNU
90
V
DD
7
DQ4
49
V
DD
91
DQ36
8
DQ5
50
NC
92
DQ37
9
DQ6
51
NC
93
DQ38
10
DQ7
52
NC
94
DQ39
11
DQ8
53
NC
95
DQ40
12
V
SS
54
V
SS
96
V
SS
13
DQ9
55
DQ16
97
DQ41
14
DQ10
56
DQ17
98
DQ42
15
DQ11
57
DQ18
99
DQ43
16
DQ12
58
DQ19
100
DQ44
17
DQ13
59
V
DD
101
DQ45
18
V
DD
60
DQ20
102
V
DD
19
DQ14
61
NC
103
DQ46
20
DQ15
62
NC
104
DQ47
21
NC
63
CKE1*
105
NC
22
NC
64
V
SS
106
NC
23
V
SS
65
DQ21
107
V
SS
24
NC
66
DQ22
108
NC
25
NC
67
DQ23
109
NC
26
V
DD
68
V
SS
110
V
DD
27
WE#
69
DQ24
111
CAS#
28
DQMB0
70
DQ25
112 DQMB4
29
DQMB1
71
DQ26
113 DQMB5
30
S0#
72
DQ27
114
S1#*
31
DNU
73
V
DD
115
RAS#
32
V
SS
74
DQ28
116
V
SS
33
A0
75
DQ29
117
A1
34
A2
76
DQ30
118
A3
35
A4
77
DQ31
119
A5
36
A6
78
V
SS
120
A7
37
A8
79
CK2
121
A9
38
A10
80
NC
122
BA0
39
BA1
81 NC/WP**
123
A11
40
V
DD
82
SDA
124
V
DD
41
V
DD
83
SCL
125
CK1
42
CK0
84
V
DD
126
RFU
*128MB version only
**-133/-10E versions only
PIN SYMBOL
127
V
SS
128
CKE0
129
S3#*
130 DQMB6
131 DQMB7
132
RFU
133
V
DD
134
NC
135
NC
136
NC
137
NC
138
V
SS
139
DQ48
140
DQ49
141
DQ50
142
DQ51
143
V
DD
144
DQ52
145
NC
146
NC
147
NC
148
V
SS
149
DQ53
150
DQ54
151
DQ55
152
V
SS
153
DQ56
154
DQ57
155
DQ58
156
DQ59
157
V
DD
158
DQ60
159
DQ61
160
DQ62
161
DQ63
162
V
SS
163
CK3
164
NC
165
SA0
166
SA1
167
SA2
168
V
DD
8, 16 Meg x 64 SDRAM DIMMs
ZM06_5.p65 – Rev. 3/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
Micron is a registered trademark of Micron Technology, Inc.
8, 16 MEG x 64
SDRAM DIMMs
PART NUMBERS
PART NUMBER
MT8LSDT864AG-13E_
MT8LSDT864AG-133_
MT8LSDT864AG-10E_
MT8LSDT864AG-662_
MT16LSDT1664AG-13E_
MT16LSDT1664AG-133_
MT16LSDT1664AG-10E_
MT16LSDT1664AG-662_
MT8LSDT864AI-133_
MT8LSDT864AI-10E_
MT8LSDT864AI-662_
MT16LSDT1664AI-133_
MT16LSDT1664AI-10E_
MT16LSDT1664AI-662_
CONFIG
8 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
8 Meg x 64
8 Meg x 64
8 Meg x 64
16 Meg x 64
16 Meg x 64
16 Meg x 64
BUS SPEED
TEMP
133 MHz
0
o
to +70
o
133 MHz
0
o
to +70
o
100 MHz
0
o
to +70
o
66 MHz
0
o
to +70
o
133MHz
0
o
to +70
o
133 MHz
0
o
to +70
o
100 MHz
0
o
to +70
o
66 MHz
0
o
to +70
o
133 MHz -40
o
to +85
o
100 MHz -40
o
to +85
o
66 MHz -40
o
to +85
o
133 MHz -40
o
to +85
o
100 MHz -40
o
to +85
o
66 MHz -40
o
to +85
o
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes. Example:
MT8LSDT864AG-10EB4.
GENERAL DESCRIPTION
The MT8LSDT864A and MT16LSDT1664A are high-
speed CMOS, dynamic random-access, 64MB and 128MB
memories organized in a x64 configuration. These
modules use internally configured quad-bank SDRAMs
with a synchronous interface (all signals are registered
on the positive edge of the clock signals CK0-CK3).
Read and write accesses to the SDRAM modules are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the bank and row to be accessed (BA0, BA1
select the bank, A0-A11 select the row). The address bits
registered coincident with the READ or WRITE com-
mand are used to select the starting column location for
the burst access.
These modules provide for programmable READ or
WRITE burst lengths of 1, 2, 4 or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
These modules use an internal pipelined architec-
ture to achieve high-speed operation. This architecture
is compatible with the 2n rule of prefetch architectures,
but it also allows the column address to be changed on
every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing one of the
other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access opera-
tion.
These modules are designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
SDRAM modules offer substantial advances in DRAM
operating performance, including the ability to syn-
chronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access. For
more information regarding SDRAM operation, refer to
the 64Mb x4, x8, x16 SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM’s
SCL (clock) and SDA (data) signals, together with SA(2:0),
which provide eight unique DIMM/EEPROM addresses.
8, 16 Meg x 64 SDRAM DIMMs
ZM06_5.p65 – Rev. 3/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8, 16 MEG x 64
SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT8LSDT864A (64MB)
S0#
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
S2#
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RAS#
CAS#
CKE0
WE#
A0-A11
BA0
BA1
V
DD
V
SS
DQM CS#
DQ0
DQ1 U9
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM CS#
DQ0
DQ1 U8
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U6
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U3
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM CS#
DQ0
DQ1 U4
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS#: SDRAMs U0-U7
CAS#: SDRAMs U0-U7
CKE0: SDRAMs U0-U7
WE#: SDRAMs U0-U7
A0-A11: SDRAMs U0-U7
BA0: SDRAMs U0-U7
BA1: SDRAMs U0-U7
SDRAMs U0-U7
SDRAMs U0-U7
SPD
CK2, CK3
CK1
CK0
U0
U4
U1
U5
U2
U6
U3
U7
CK0
3.3pF
CK2
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
3.3pF
CK1, CK3
10pF
SCL
WP
47K
U10
A0 A1 A2
SA0 SA1 SA2
SDA
10pF
100 MHz/133 MHz VERSIONS
66 MHz VERSION
U0-U7 = MT48LC8M8A2GT SDRAMs
NOTE:
All resistor values are 10 ohms.
8, 16 Meg x 64 SDRAM DIMMs
ZM06_5.p65 – Rev. 3/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8, 16 MEG x 64
SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT16LSDT1664A (128MB)
S0#
S1#
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
S2#
S3#
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
V
DD
10K
DQMB4
DQM CS#
DQ0
DQ1 U1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U3
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U19
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U17
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM CS#
DQ0
DQ1 U4
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U16
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U18
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB6
DQM CS#
DQ0
DQ1 U7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U9
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U13
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U11
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM CS#
DQ0
DQ1 U8
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U12
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U6
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM CS#
DQ0
DQ1 U14
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CKE1
CKE0
CAS#
RAS#
WE#
A0-A11
BA0
BA1
V
DD
V
SS
CKE: SDRAMs U8-U15
CKE: SDRAMs U0-U7
CAS#: SDRAMs U0-U15
RAS#: SDRAMs U0-U15
WE#: SDRAMs U0-U15
A0-A11: SDRAMs U0-U15
BA0: SDRAMs U0-U15
BA1: SDRAMs U0-U15
SDRAMs U0-U15
SDRAMs U0-U15
SPD
CK3
CK2
CK1
CK0
SDRAM
SDRAM
SDRAM
SDRAM
3.3pF
SDRAM
SDRAM
SDRAM
SDRAM
3.3pF
SDRAM
SDRAM
SDRAM
SDRAM
3.3pF
SDRAM
SDRAM
SDRAM
SDRAM
SCL
WP
47K
A0
A1
A2
SDA
3.3pF
U0-U15 = MT48LC8M8A2TG SDRAMs
SA0 SA1 SA2
NOTE:
All resistor values are 10 ohms unless otherwise specified.
8, 16 Meg x 64 SDRAM DIMMs
ZM06_5.p65 – Rev. 3/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
8, 16 MEG x 64
SDRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
115, 111, 27
42, 79, 125, 163
SYMBOL
RAS#, CAS#,
WE#
CK0-CK3
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS# and WE# (along with
S0#-S3#) define the command being entered.
Clock: CK0-CK3 are driven by the system clock. All SDRAM
input signals are sampled on the positive edge of CK. CK
also increments the internal burst counter and controls
the output registers.
Clock Enable: CKE0-CKE1 activate (HIGH) and deactivate
(LOW) the CK0-CK3 signals. Deactivating the clock provides
PRECHARGE POWER-DOWN and SELF REFRESH operation
(all banks idle), ACTIVE POWER-DOWN (row ACTIVE in any
bank) or CLOCK SUSPEND operation (burst access in
progress). CKE0-CKE1 are synchronous except after the
device enters power-down and self refresh modes, where
CKE0-CKE1 become asynchronous until after exiting the
same mode. The input buffers, including CK0-CK3, are
disabled during power-down and self refresh modes,
providing low standby power.
Chip Select: S0#-S3# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S0#-S3# are registered HIGH. S0#-S3# are
considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses.
Input data is masked when DQMB is sampled HIGH during
a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when DQMB is sampled HIGH
during a READ cycle.
Bank Address: BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE com-
mand (column-address A0-A8, with A10 defining AUTO
PRECHARGE) to select one location out of the memory
array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1
(LOW). The address inputs also provide the op-code during
a LOAD MODE REGISTER command.
Write Protect: Serial presence-detect hardware write
protect. Applies to -10E/-10C versions only.
Serial Clock for Presence-Detect: SCL is used to synchro-
nize the presence-detect data transfer to and from the
module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
63, 128
CKE1, CKE0
Input
30, 45, 114, 129
S0#-S3#
Input
28-29, 46-47,
112-113, 130-131
DQMB0-DQMB7
Input
39, 122
BA0, BA1
Input
33-38, 117-121, 123
A0-A11
Input
81
83
WP
SCL
Input
Input
165-167
SA0-SA2
Input
8, 16 Meg x 64 SDRAM DIMMs
ZM06_5.p65 – Rev. 3/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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