Product Specification
PE3342
Product Description
Peregrine’s PE3342 is a high performance integer-N PLL with
embedded EEPROM capable of frequency synthesis up to
2700 MHz with a speed-grade option to 3000 MHz. The
EEPROM allows designers to permanently store control bits,
allowing easy configuration of self-starting synthesizers. The
superior phase noise performance of the PE3342 is ideal for
applications such as wireless base stations, fixed wireless, and
RF instrumentation systems.
The PE3342 features a ÷10/11 dual modulus prescaler,
counters, and a phase comparator as shown in Figure 1.
Counter values are programmable through a three-wire serial
interface.
The PE3342 UltraCMOS™ Phase Locked-Loop is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi®) CMOS process, offering excellent RF performance
with the economy and integration of conventional CMOS.
2.7 GHz Integer-N PLL
with Field-Programmable EEPROM
Features
•
Field-programmable EEPROM for self-
starting applications
•
Standard 2700 MHz operation,
3000 MHz speed-grade option
•
÷10/11 dual modulus prescaler
•
Internal phase detector
•
Serial programmable
•
Low power — 20 mA at 3 V
•
Ultra-low phase noise
•
Available in 20-lead 4x4 mm QFN
package
Figure 1. Block Diagram
F
in
F
in
ENH
E_WR
Data
Clock
Serial
Interface
Mux
Enhancement
Register
(8-bit)
Primary
Register
(20-bit)
EE
Register
(20-bit)
Prescaler
÷10/11
M Counter
÷2 to ÷512
13
20
Secondary
Register
(20-bit)
Phase
Detector
PD_U
PD_D
20
6
20
LD
2k
6
Cext
EELoad
Transfer
Logic
V
PP
S_WR
f
r
EESel
FSel
EEPROM
R Counter
÷1 to ÷64
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Page 1 of 17
PE3342
Product Specification
Figure 2. Pin Configuration (Top View)
EESel
PD_U
ENH
V
DD
Figure 3. Package Type
20-lead QFN
20
19
18
f
r
17
S_WR
Data
Clock
FSel
E_WR
16
1
2
3
4
5
15
PD_D
V
DD
Dout
LD
EELoad
20-lead QFN
4x4mm
Exposed Solder Pad
(Bottom Side)
14
13
12
11
F
IN
V
DD
V
PP
F
IN
Table 2. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
S_WR
Data
Clock
FSel
E_WR
V
PP
V
DD
F
in
F
in
C
EXT
EELoad
LD
Dout
V
DD
PD_D
PD_U
EESel
f
r
V
DD
ENH
C
EXT
10
6
7
8
9
Type
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Output
Input
Output, OD
Output
(Note 1)
Output
Output
Input
Input
(Note 1)
Input
Description
Secondary Register WRITE input. Primary Register contents are copied to the Secondary Register on
S_WR rising edge. Also used to control Serial Port operation and EEPROM programming.
Binary serial data input. Input data entered LSB (B
0
) first.
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE Register, or
the 8-bit Enhancement Register on the rising edge of Clock. Also used to clock EE Register data out
Dout port.
Frequency Register selection control line. Internal 70 kW pull-down resistor.
Enhancement Register write enable. Also functions as a Serial Port control line. Internal 70 kW pull-
down resistor.
EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass capacitor connected
to GND.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Prescaler input from the VCO.
Prescaler complementary input. A series 50 W resistor and DC blocking capacitor should be placed as
close as possible to this pin and connected to the ground plane.
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kW series resistor. Connecting
C
EXT
to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Control line for Serial Data Port, Frequency Register selection, EE Register parallel loading, and
EEPROM programming. Internal 70 kW pull-down resistor.
Lock detect output, an open-drain logical inversion of C
EXT
. When the loop is in lock, LD is high
impedance; otherwise, LD is a logic LOW.
Data out function. Dout is defined with the Enhancement Register and enabled with ENH.
Same as pin 7.
Phase detector output. PD_D pulses negatively when fp leads fc.
Phase detector output. PD_U pulses negatively when fc leads fp.
Control line for Frequency Register selection, EE Register parallel loading, and EEPROM
programming. Internal 70 kW pull-up resistor.
Reference frequency input.
Same as pin 7.
Enhancement mode control line. When asserted LOW, enhancement register bits are functional.
Internal 70 kW pull-up resistor.
Notes 1:
V
DD
pins 7, 14 and 19 are connected by diodes and must be supplied with the same positive voltage level.
2:
Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation.
©2005-8 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 17
Document No. 70-0091-04
│
UltraCMOS™ RFIC Solutions
PE3342
Product Specification
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
Stg
Table 5. ESD Ratings
Units
V
V
°C
Parameter/Conditions
Supply voltage
Voltage on any digital
input
Storage temperature
range
Min
–0.3
–0.3
–65
Max
+4.0
V
DD
+0.3
+85
Symbol
V
ESD
V
ESD
(V
PP
)
Parameter/Conditions
ESD voltage human body
model (Note 1)
ESD voltage human body
model (Note 1)
Min
Max
1000
200
Units
V
V
Note 1:
Periodically sampled, not 100% tested. Tested per MIL-
STD-883, M3015 C2
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating in Table 4.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 4. Operating Ranges
Symbol
V
DD
T
A
Parameter/Conditions
Supply voltage
Operating ambient
temperature range
Min
2.85
-40
Max
3.15
85
Units
V
°C
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Page 3 of 17
PE3342
Product Specification
Table 6. DC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
Prescaler enabled
Digital Inputs: S_WR, Data, Clock
V
IH
V
IL
I
IH
I
IL
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
I
DD
Parameter
Operational supply current;
Conditions
V
DD
= 2.85 to 3.15 V
Min
Typ
20
Max
30
Units
mA
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
0.7 x V
DD
0.3 x V
DD
+1
-1
V
V
µA
µA
Digital inputs: ENH, EESel (contains a 70 kΩ pull-up resistor)
V
IH
V
IL
I
IH
I
IL
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-100
0.7 x V
DD
0.3 x V
DD
+1
V
V
µA
µA
Digital inputs: FSel, EELoad, E_WR (contains a 70 kΩ pull-down resistor)
V
IH
V
IL
I
IH
I
IL
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
V
DD
= 2.85 to 3.15 V
V
DD
= 2.85 to 3.15 V
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-1
0.7 x V
DD
0.3 x V
DD
+100
V
V
µA
µA
EE Memory Programming Voltage and Current: V
PP
, I
PP
V
PP
_WRITE
V
PP
_ERASE
I
PP
_WRITE
I
PP
_ERASE
EEPROM write voltage
EEPROM erase voltage
EEPROM write cycle current
EEPROM erase cycle current
-10
12.5
-8.5
30
V
V
mA
mA
Reference Divider input: f
r
I
IHR
I
ILR
High-level input current
Low-level input current
V
IH
= V
DD
= 3.15 V
V
IL
= 0, V
DD
= 3.15 V
-100
+100
µA
µA
Counter output: Dout
V
OLD
V
OHD
Output voltage LOW
Output voltage HIGH
I
out
= 6 mA
I
out
= -3 mA
V
DD
- 0.4
0.4
V
V
Lock detect outputs: (C
EXT
, LD)
V
OLC
V
OHC
V
OLLD
Output voltage LOW, C
EXT
Output voltage HIGH, C
EXT
Output voltage LOW, LD
I
out
= 0.1 mA
I
out
= -0.1 mA
I
out
= 1 mA
V
DD
- 0.4
0.4
0.4
V
V
V
©2005-8 Peregrine Semiconductor Corp. All rights reserved.
Page 4 of 17
Document No. 70-0091-04
│
UltraCMOS™ RFIC Solutions
PE3342
Product Specification
Table 7. AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
t
EESU
t
EEPW
t
VPP
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Data set-up time to Clock rising edge
Data hold time after Clock rising edge
S_WR pulse width
Clock rising edge to S_WR rising edge
Clock falling edge to E_WR transition
S_WR falling edge to Clock rising edge
E_WR transition to Clock rising edge
(Note 1)
Conditions
Min
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface and Registers (see Figure 4)
30
30
10
10
30
30
30
30
30
EEPROM Erase/Write Programming (see Figures 5 & 6)
EELoad rising edge to V
PP
rising edge
V
PP
pulse width
V
PP
pulse rise and fall times
(Note 2)
500
25
1
30
ms
µs
Main Divider (Including Prescaler)
F
In
F
In
P
FIn
Operating frequency
Operating frequency
Input level range
Speed-grade option (Note 3)
External AC coupling
300
300
-5
2700
3000
5
MHz
MHz
dBm
Main Divider (Prescaler Bypassed)
F
In
P
FIn
Operating frequency
Input level range
(Note 4)
External AC coupling (Note 4)
50
-5
270
5
MHz
dBm
Reference Divider
f
r
P
fr
Phase Detector
f
c
Comparison frequency
(Note 6)
20
MHz
Operating frequency
Reference input power (Note 4)
(Note 5)
Single ended input
-2
100
MHz
dBm
SSB Phase Noise (F
in
= 1.3 GHz, f
r
= 10 MHz, f
c
= 1.25 MHz, LBW = 70 kHz, V
DD
= 3.0 V, Temp = -40° C
)
100 Hz Offset
1 kHz Offset
Note 1:
Note 2:
Note 3:
Note 4:
-75
-85
dBc/Hz
dBc/Hz
f
Clk
is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify f
Clk
specification.
Rise and fall times of the V
PP
programming voltage pulse must be greater than 1
µs.
The maximum frequency of operation can be extended to 3.0 GHz by ordering a special speed-grade option. Please refer to Table 14,
Ordering Information, for ordering details.
CMOS logic levels can be used to drive F
In
input if DC coupled and used in Prescaler Bypass mode. Voltage input needs to be a minimum
of 0.5 Vp-p. For optimum phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns. No minimum
frequency limit exists when operated in this mode.
Note 5:
Note 6:
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum
phase noise performance, the reference input falling edge rate should be faster than 80 mV/ns.
Parameter is guaranteed through characterization only and is not tested.
©2005-8 Peregrine Semiconductor Corp. All rights reserved.
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