8Gb: x16, x32 GDDR5X SGRAM
Features
GDDR5X SGRAM
MT58K256M321JA-100/-110/-120:A
16 Meg x 32 I/O x 16 banks, 32 Meg x 16 I/O x 16 banks
Features
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V
DD
= V
DDQ
= 1.35V ±3%
V
PP
= 1.8V -3%/+6%
Data rate: 12.0 Gb/s, 11.0 Gb/s, 10.0 Gb/s
Single ended interface for command, address and
data
Differential clock input CK_t/CK_c for ADD/CMD
Two differential clock inputs WCK_t/WCK_c, each
associated with two data bytes (DQ, DBI_n, EDC)
Single data rate (SDR) commands (CK)
Double data rate (DDR) addresses (CK)
QDR and DDR operating modes:
– QDR mode: Quad data rate (QDR) data (WCK);
16n prefetch architecture with 512bit per array
read or write access; burst length 16
– DDR mode: Double data rate (DDR) data (WCK);
8n prefetch architecture with 256bit per array
read or write access; burst length 8
16 internal banks
4 bank groups for
t
CCDL = 3
t
CK and 4
t
CK
Programmable READ latency: 9 to 20
Programmable WRITE latency: 5 to 7
Write data mask function via address bus (single/
double/quad byte mask)
Data bus inversion (DBI) and address bus inversion
(ABI)
Input/output PLL
Address training: Address input monitoring via DQ/
DBI_n/EDC pins
WCK2CK clock training with phase information via
EDC pins
Data read and write training via read FIFO (depth =
6)
Read FIFO pattern preload by LDFF command
Write data load to read FIFO via WRTR command
Consecutive read of read FIFO via RDTR command
Read/write EDC on/off mode
Programmable EDC hold pattern for CDR
Read/write data transmission integrity secured by
cyclic redundancy check (CRC‐8)
Programmable CRC READ latency = 2 to 3
Programmable CRC WRITE latency = 9 to 14
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Low power modes
RDQS mode on EDC pins
On‐chip temperature sensor with read‐out
Auto precharge option for each burst access
Auto refresh mode with per-bank refresh option
Temperature sensor controlled self refresh rate
Digital
t
RAS lockout
On‐die termination (ODT) for all high‐speed inputs
Pseudo open drain (POD‐135) compatible outputs
ODT and output driver strength auto‐calibration
with external resistor ZQ pin (120
Ω)
Programmable termination and driver strength off-
sets
Internal V
REF
for data inputs
Selectable external or internal V
REF
for ADD/CMD
inputs
Data input receiver characteristics programmable
per byte
Vendor ID for device identification
Mirror function with MF pin
IEEE 1149.1 compliant boundary scan
190 ball BGA package
Lead-free (RoHS-compliant) and halogen-free
packaging
T
C
= 0°C to +95°C
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Options
1
• Organization
– 256 Meg x 32 (words x bits)
• FBGA package
– 190-ball (10mm x 14mm)
• Timing – maximum data rate
– 12.0 Gb/s
– 11.0 Gb/s
– 10.0 Gb/s
• Operating temperature
– Commercial (0°C
≤
T
C
≤
+95°C)
• Revision
Note:
Marking
256M321
JA
-120
-110
-100
None
A
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on
http://www.micron.com
for available offerings.
CMTD-1412786195-10190
gddr5x_sgram_8gb_mt58k256m321.pdf - Rev. C 2/17 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2016 Micron Technology, Inc. All rights reserved.
8Gb: x16, x32 GDDR5X SGRAM
Features
Figure 1: Part Numbering
MT58K 256M321 JA -120 : A
Micron Memory
Configuration
256M321 = 256 Meg x 32
Package
JA = 190-ball FBGA, 10.00mm x 14.00mm
Revision A
Temperature
: = Commercial
Data Rate
-120 = 12.0 Gb/s
-110 = 11.0 Gb/s
-100 = 10.0 Gb/s
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s web site:
http://www.micron.com.
CMTD-1412786195-10190
gddr5x_sgram_8gb_mt58k256m321.pdf - Rev. C 2/17 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2016 Micron Technology, Inc. All rights reserved.
8Gb: x16, x32 GDDR5X SGRAM
Operating Frequency Ranges
Operating Frequency Ranges
Figure 2: Data Rates in QDR, DDR, and RDQS Modes
MT58K256M321JA-100:A
QDR Mode
DDR Mode
RDQS Mode
0.2
2.0
4.0
5.5 6.0
8.0
10.0
[Gbps/pin]
MT58K256M321JA-110:A
QDR Mode
DDR Mode
RDQS Mode
0.2
2.0
4.0
5.5 6.0
8.0
10.0
11.0
[Gbps/pin]
MT58K256M321JA-120:A
QDR Mode
DDR Mode
RDQS Mode
0.2
2.0
4.0
6.0
8.0
10.0
12.0 [Gbps/pin]
Table 1: Operating Frequency Ranges
-100
Operating Mode
QDR mode
DDR mode
RDQS mode
Symbol
f
CK
-110
Max
1250
1375
500
Min
687
50
50
Max
1375
1375
500
Min
750
50
50
-120
Max
1500
1500
500
Unit
MHz
Min
687
50
50
Note:
The operating range and AC timings of a faster speed bin are a superset of all
slower speed bins. Therefore it is safe to use a faster bin device as a drop-in replacement
of a slower bin device when operated within the frequency range of the slower bin de-
vice.
CMTD-1412786195-10190
gddr5x_sgram_8gb_mt58k256m321.pdf - Rev. C 2/17 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2016 Micron Technology, Inc. All rights reserved.
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