NB7L216
2.5 V / 3.3 V, 12Gb/s Multi
Level Clock/Data Input to
RSECL, High Gain
Receiver/Buffer/Translator
with Internal Termination
Description
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A
L
Y
W
G
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Gain of 35 dB from DC to 7 GHz Typical
High IIP3: 0 dBm Typical
20 mV Minimum Input Voltage Swing
Maximum Input Clock Frequency up to 8.5 GHz
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 9 ps of Data Dependent Jitter
120 ps Typical Propagation Delay
30 ps Typical Rise and Fall Times
RSPECL Output with Operating Range:
V
CC
= 2.375 V to 3.465 V with V
EE
= 0 V
RSNECL Output with RSNECL or NECL Inputs with Operating
Range: V
CC
= 0 V with V
EE
=
−2.375
V to
−3.465
V
RSECL Output Level (400 mV Peak-to-Peak Output),
50
W
Internal Input Termination Resistors (Temperature-Coefficient
of < 6.38 mW/°C)
V
BB
– ECL Reference Voltage Output
This Device is Pb-Free, Halogen Free and is RoHS Compliant
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note
AND8002/D.
VTD
50
W
D
D
50
W
VTD
Q
Q
Figure 1. Functional Block Diagram
ORDERING INFORMATION
Device
NB7L216MNG
NB7L216MNR2G
Package
QFN−16
(Pb-Free)
QFN−16
(Pb-Free)
Shipping†
123 Units / Tube
3000 Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
August, 2016
−
Rev. 6
1
ÇÇÇ
ÇÇÇ
1
The NB7L216 is a differential receiver/driver with high gain output
targeted for high frequency applications. The device is functionally
equivalent to the NBSG16 but with much higher gain output. This
highly versatile device provides 35 dB of gain up to 7 GHz.
Inputs incorporate internal 50
W
termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are Reduced Swing ECL (RSECL), 400 mV.
The V
BB
pin is an internally generated voltage supply available to
this device only. V
BB
is used as a reference voltage for single-ended
NECL or PECL inputs. For all single-ended input conditions, the
unused complementary differential input should be connected to V
BB
as a switching reference voltage. V
BB
may also rebias AC coupled
inputs. When used, decouple V
BB
via a 0.01
mF
capacitor and limit
current sourcing or sinking to 0.5 mA. When not used, V
BB
output
should be left open.
Application notes, models and support documentation are available
at
www.onsemi.com.
1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
16
NB7L
216
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb-Free Package
Publication Order Number:
NB7L216/D
NB7L216
V
EE
16
VTD
D
D
VTD
1
2
NB7L216
3
4
5
V
EE
6
7
8
V
BB
15
V
EE
V
EE
Exposed Pad (EP)
14
13
12 V
CC
11 Q
10 Q
9
V
CC
VOLTAGE (60 mV/div)
Device DDJ = 3 ps
TIME (17 ps/div)
V
EE
V
EE
V
EE
Figure 2. QFN-16 Pinout
(Top View)
Figure 3. Typical Output Waveform at
12 Gb/s with PRBS 2
23
−1
(V
INPP
= 400 mV,
Input Signal DDJ = 12 ps)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
VTD
D
I/O
−
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
LVPECL, CML,
LVCMOS, LVDS,
LVTTL Input
−
−
−
−
RSECL Output
RSECL Output
−
Description
Internal 50
W
termination pin. See Table 7. Note 1
Inverted differential input. Note 1.
3
D
Noninverted differential input. Note 1.
4
15
5, 6, 7, 8, 13, 14, 16
9, 12
10
11
−
VTD
V
BB
V
EE
V
CC
Q
Q
EP
Internal 50
W
termination pin. See Table 7. Note 1.
Internally generated ECL reference voltage supply.
Negative supply voltage. All V
EE
pins must be externally connected to power
supply to guarantee proper operation.
Positive supply voltage. All V
CC
pins must be externally connected to power
supply to guarantee proper operation
Noninverted differential output. Typically receiver terminated with 50
W
resistor
to V
TT
= V
CC
−
2.0 V.
Inverted differential output. Typically receiver terminated with 50
W
resistor to
V
TT
= V
CC
−
2.0 V.
Exposed pad (EP). Thermally exposed pad on the package bottom must be
attached to a heat sinking conduit. It is recommended to connect the EP to the
lower potential, V
EE
.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage and if no signal
is applied on D/D input then the device will be susceptible to self-oscillation.
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2
NB7L216
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity (Note 2)
QFN−16
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.
1. For additional information, see Application Note
AND8003/D.
Oxygen Index: 28 to 34
Value
> 500 V
> 10 V
> 4 kV
Pb-Free Pkg
Level 1
UL 94 V−0 @ 0.125 in
164
Table 3. MAXIMUM RATINGS
(Note 1)
Symbol
V
CC
V
EE
V
I
V
INPP
I
IN
I
OUT
I
BB
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage
|D
−
D|
Static
Surge
Continuous
Surge
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
I
= V
CC
V
I
= V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
45
80
25
50
±0.5
−40
to +85
−65
to +150
0 lfpm
500 lfpm
1S2P (Note 4)
QFN−16
QFN−16
QFN−16
42
35
4
265
Unit
V
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C
Input Current Through R
T
(50
W
Resistor)
Output Current
V
BB
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
(Note 2)
Thermal Resistance (Junction-to-Case)
Wave Solder (Pb-Free)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously.
If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board
−
1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB7L216
Table 4. DC CHARACTERISTICS, CLOCK INPUTS, RSECL OUTPUTS
(V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V)
−40
5C
Symbol
I
EE
V
OH
V
OL
Characteristic
Power Supply Current
(VTD/VTD open)
Output HIGH Voltage
(Note 1 and 2)
Output LOW Voltage
(Note 1 and 2)
V
CC
−1040
V
CC
−1520
Min
Typ
27
V
CC
−980
V
CC
−1430
Max
35
V
CC
−940
V
CC
−1320
V
CC
−1000
V
CC
−1470
Min
25
5C
Typ
27
V
CC
−950
V
CC
−1370
Max
35
V
CC
−900
V
CC
−1270
V
CC
–950
V
CC
–1440
Min
85
5C
Typ
27
V
CC
−900
V
CC
−1340
Max
35
V
CC
−850
V
CC
−1240
Unit
mA
mV
mV
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED
(see Figures 14 and 16)
V
TH
V
IH
V
IL
V
ISE
Input Threshold Reference Voltage
Range (Notes 3 and 5)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Single-Ended Input Voltage
(V
IH
–V
IL
)
800
1105
V
EE
20
V
CC
−10
V
CC
V
th
−10
V
CC
800
1105
V
EE
20
V
CC
−10
V
CC
V
th
−10
V
CC
800
1105
V
EE
20
V
CC
−10
V
CC
V
th
−10
V
CC
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(see Figures 15 and 17)
V
IHD
V
ILD
V
CMR
Differential Input HIGH Voltage
(Note 5)
Differential Input LOW Voltage
(Note 5)
Input Common Mode Range
(Differential Configuration,
Notes 5 and 6)
Differential Input Voltage
(V
IHD
−V
ILD
)
Input Offset Voltage (Note 4)
Internally Generated Reference
Voltage Supply
(Only 3 V – 3.6 V Supply Load with
−100
mA)
Input HIGH Current
D/Db (VTD/VTD Open)
Input LOW Current
D/Db (VTD/VTD Open)
Internal Input Termination Resistor
Internal Input Termination Resistor
Temperature Coefficient
1105
V
EE
800
V
CC
V
CC
−10
V
CC
−5
2500
0
V
CC
−1345
+5
V
CC
−1265
1105
V
EE
800
V
CC
V
CC
−10
V
CC
–5
2500
0
V
CC
−1345
+5
V
CC
−1265
1105
V
EE
800
V
CC
V
CC
−10
V
CC
–5
2500
0
V
CC
−1345
+5
V
CC
−1265
mV
mV
mV
V
ID
V
IO
V
BB
10
−5
V
CC
−1425
10
−5
V
CC
−1425
10
−5
V
CC
−1425
mV
mV
mV
I
IH
I
IL
R
TIN
R
T_Coef
0
−25
45
20
10
50
6.38
100
75
55
0
−25
45
20
10
50
6.38
100
75
55
0
−25
45
20
10
50
6.38
100
75
55
mA
mA
W
mW/°C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
1. Outputs evaluated with 50
W
resistors to V
TT
= V
CC
−
2.0 V for proper operation.
2. Input and output parameters vary 1:1 with V
CC
.
3. V
TH
is applied to the complementary input when operating in single−ended mode. V
th
= (V
IH
−
V
IL
) / 2.
4. Typical standard deviation of input offset voltage is 1.76 mV.
5. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
6. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
7. V
CMR
min varies 1:1 with V
EE
, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential input
signal.
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4
NB7L216
Table 5. AC CHARACTERISTICS
(V
CC
= 2.375 V to 3.465 V, V
EE
= 0 V; (Note 1))
−40°C
Symbol
V
OUTPP
Characteristic
Output Voltage Amplitude (@ V
INPPmin
)
f
in
≤
7.0 GHz
f
in
≤
8.5 Ghz (See Figure 4)
Maximum Operating Data Rate
Power Gain DC to 7 GHz
Input Return Loss @ 7 GHz
Output Return Loss @ 7 GHz
Reverse Isolation (Differential Configuration)
Input Third Order Intercept
Propagation Delay to Output Differential @ 1 GHz
Duty Cycle Skew (Note 1)
Device to Device Skew (Note 6)
RMS Random Clock Jitter
f
in
v
8.5 Ghz (Note 4)
Peak-to-Peak Data Dependent Jitter (Note 5)
f
DATA
= 3.5 Gb/s
f
DATA
= 5.0 Gb/s
f
DATA
= 10 Gb/s
f
DATA
= 12 Gb/s
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 3 and Figure 12)
Output Rise/Fall Times @ 0.5 Ghz (20%
−
80%)
Q, Q
20
60
Min
275
100
10
Typ
380
250
12
35
−10
−5
−25
0
120
2
5
0.1
1
3
4
4
180
10
20
0.5
7
9
9
9
2500
20
60
Max
Min
275
100
10
25°C
Typ
380
250
12
35
−10
−5
−25
0
120
2
5
0.1
1
3
4
4
180
10
20
0.5
7
9
9
9
2500
20
60
Max
Min
275
100
10
85°C
Typ
380
250
12
35
−10
−5
−25
0
120
2
5
0.1
1
3
4
4
180
10
20
0.5
7
9
9
9
2500
mV
ps
Max
Unit
mV
f
DATA
|S21|
|S11|
|S22|
|S12|
IIP3
t
PLH
,
t
PHL
t
SKEW
t
JITTER
Gb/s
dB
dB
dB
dB
dBm
ps
ps
ps
V
INPP
t
r
t
f
30
45
30
45
30
45
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values
are applied individually under normal operating conditions and not valid simultaneously.
1. Measured by forcing V
INPPmin
from a 50% duty cycle clock source. All loading with an external R
L
= 50
W
to V
TT
=V
CC
−
2.0 V. Input edge
rates 40 ps (20%− 80%).
2. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 1 GHz.
3. V
INPP
(MAX) cannot exceed V
CC
−
V
EE
. Input voltage swing is a single-ended measurement operating in differential mode.
4. Additive RMS jitter with 50% duty cycle clock signal.
5. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 2
23
−1.
6. Device to device skew is measured between outputs under identical transition @ 1 GHz.
OUTPUT VOLTAGE AMPLITUDE (mV)
OUTPUT VOLTAGE AMPLITUDE (mV)
500
450
400
350
300
250
200
150
100
50
0
0
2
4
6
7
8
9
10
INPUT CLOCK FREQUENCY (GHz)
11
12
85°C
25°C
−40°C
500
450
400
350
300
250
200
150
100
50
0
0
2
4
6
7
8
9
10
INPUT CLOCK FREQUENCY (GHz)
11
12
85°C
25°C
−40°C
Figure 4. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
IN
) and Temperature
(V
INPP
= 400 mV, V
CC
= 3.3 V and V
EE
= 0 V)
Figure 5. Output Voltage Amplitude (V
OUTPP
) versus
Input Clock Frequency (f
IN
) and Temperature
(V
INPP
= 20 mV, V
CC
= 3.3 V and V
EE
= 0 V)
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