FEMTOCLOCK™ CRYSTAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
ICS840021
General Description
The ICS840021 is a Gigabit Ethernet Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from IDT. The
ICS840021 uses a 25MHz crystal to synthesize
125MHz. The ICS840021 has excellent phase jitter
performance, over the 1.875MHz – 20MHz integration range. The
ICS840021 is packaged in a small 8-pin TSSOP, making it ideal for
use in systems with limited board space.
Features
•
•
•
•
•
•
•
One LVCMOS/LVTTL output, 7Ω output impedance
Crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal
Output frequency: 125MHz
VCO range: 560MHz to 680MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.34ps (typical) 3.3V
RMS phase noise at 125MHz (typical)
Phase noise:
Offset
Noise Power
100Hz ................-96.9 dBc/Hz
1kHz ..............-122.2 dBc/Hz
10kHz ..............-131.1 dBc/Hz
100Hz ..............-129.5 dBc/Hz
ICS
•
•
•
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
OE
Pullup
25MHz
Pin Assignment
V
DDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q0
GND
RESERVED
XTAL_IN
XTAL_OUT
OSC
Phase
Detector
VCO
÷5
Q0
ICS840021
÷25
(fixed)
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm package body
G Package
Top View
IDT™ / ICS™
LVCMOS CLOCK GENERATOR
1
ICS840021AG REV. B APRIL 28, 2009
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6
7
8
Name
V
DDA
OE
XTAL_OUT,
XTAL_IN
Reserved
GND
Q0
V
DD
Type
Power
Input
Input
Reserved
Power
Output
Power
Pullup
Description
Analog supply pin.
Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to
high-impedance state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Reserve pin.
Power supply ground.
Single-ended clock output. LVCMOS/LVTTL interface levels.
7
Ω
output impedance.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 1,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Output Impedance
5
V
DD
= 3.465V
Test Conditions
Minimum
Typical
4
24
51
7
12
Maximum
Units
pF
pF
k
Ω
Ω
Function Table
Table 3. Control Function Table
Control Input
OE
0
1
Output
Q0
High-Impedance
Active
IDT™ / ICS™
LVCMOS CLOCK GENERATOR
2
ICS840021AG REV. B APRIL 28, 2009
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum
Ratings
may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
in the
DC Characteristics or AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
75
15
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
Output High Voltage; NOTE 1
Test Conditions
Minimum
2
-0.3
Typical
Maximum
Units
V
V
µA
µA
V
0.5
V
V
DD
+0.3
0.8
5
V
DD
= V
IN
= 3.465V
V
DD
=3.465V, V
IN
= 0V
-150
2.6
NOTE 1: Outputs terminated with 50Ω to V
DD
/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit"
diagram.
IDT™ / ICS™
LVCMOS CLOCK GENERATOR
3
ICS840021AG REV. B APRIL 28, 2009
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Table 5. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
Test Conditions
Minimum
Typical
Fundamental
25
50
7
1
MHz
Maximum
Units
Ω
pF
mW
AC Electrical Characteristics
Table 6. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
RMS Phase Jitter, Random;
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
Integration Range: 1.875MHz – 20MHz
20% to 80%
250
48
Test Conditions
Minimum
Typical Maximum
125
0.34
550
52
Units
MHz
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
IDT™ / ICS™
LVCMOS CLOCK GENERATOR
4
ICS840021AG REV. B APRIL 28, 2009
ICS840021
FEMTOCLOCK™CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Typical Phase Noise at 125MHz
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.34ps (typical)
←
10 Gb Ethernet Filter
Noise Power
dBc
Hz
←
Raw Phase Noise Data
Offset Frequency (Hz)
←
Phase Noise Result by adding a
10 Gb Ethernet filter to raw data
IDT™ / ICS™
LVCMOS CLOCK GENERATOR
5
ICS840021AG REV. B APRIL 28, 2009
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