Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: KL24P80M48SF0
Rev 5 08/2014
Kinetis KL24 Sub-Family
48 MHz Cortex-M0+ Based Microcontroller with USB
MKL24ZxxVFM4
MKL24ZxxVFT4
MKL24ZxxVLH4
MKL24ZxxVLK4
Designed with efficiency in mind. Compatible with all other
Kinetis L families as well as Kinetis K2x family. General purpose
MCU with USB 2.0, featuring market leading ultra low-power to
provide developers an appropriate entry-level 32-bit solution.
This product offers:
• Run power consumption down to 47 μA/MHz in very low
power run mode
• Static power consumption down to 2 μA with full state
retention and 4 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48 MHz
with industry leading throughput
• Memory option is up to 128 KB flash and 16 KB RAM
• Energy-saving architecture is optimized for low power with
90 nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
32-pin QFN (FM)
48-pin QFN (FT)
5 x 5 x 1 Pitch 0.5 mm 7 x 7 x 1 Pitch 0.5 mm
64-pin LQFP (LH)
80-pin LQFP (LK)
10 x 10 x 1.4 Pitch 0.5 12 x 12 x 1.4 Pitch 0.5
mm
mm
Performance
• 48 MHz ARM
®
Cortex
®
-M0+ core
Memories and memory interfaces
• Up to 64 KB program flash memory
• Up to 8 KB SRAM
Human-machine interface
• Up to 66 general-purpose input/output (GPIO)
Communication interfaces
• USB full-/low-speed On-the-Go controller with on-
chip transceiver and 5 V to 3.3 V regulator
• Two 8-bit SPI modules
• One low power UART module
• Two UART modules
• Two I2C module
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• 4-channel DMA controller, supporting up to 63 request
Analog Modules
sources
• 12-bit SAR ADC
• Low-leakage wakeup unit
• Analog comparator (CMP) containing a 6-bit DAC
• SWD debug interface and Micro Trace Buffer
and programmable reference input
• Bit Manipulation Engine
Clocks
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• Multi-purpose clock source
• 1 kHz LPO clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
Timers
• Six channel Timer/PWM (TPM)
• Two 2-channel Timer/PWM modules
• Periodic interrupt timers
• 16-bit low-power timer (LPTMR)
• Real time clock
Security and integrity modules
• 80-bit unique identification number per chip
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2012–2014 Freescale
Semiconductor, Inc. All rights reserved.
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
Ordering Information
Part Number
Flash (KB)
MKL24Z32VFM4
MKL24Z64VFM4
MKL24Z32VFT4
MKL24Z64VFT4
MKL24Z32VLH4
MKL24Z64VLH4
MKL24Z32VLK4
MKL24Z64VLK4
32
64
32
64
32
64
32
64
Memory
SRAM (KB)
4
8
4
8
4
8
4
8
23
23
36
36
50
50
66
66
Maximum number of I\O's
Related Resources
Type
Selector Guide
Product Brief
Reference
Manual
Data Sheet
Chip Errata
Package
drawing
Description
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Resource
Solution Advisor
The Product Brief contains concise overview/summary information to KL2 Family Product Brief
1
enable quick evaluation of a device for design suitability.
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
The Data Sheet includes electrical characteristics and signal
connections.
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
Package dimensions are provided in package drawings.
KL24P80M48SF0RM
1
KL24P80M48SF0
1
KINETIS_L_xN97F
2
QFN 32-pin: 98ASA00473D
1
QFN 48-pin: 98ASA00466D
1
LQFP 64-pin: 98ASS23234W
1
LQFP 80-pin: 98ASS23174W
1
1. To find the associated resource, go to
http://www.freescale.com
and perform a search using this term.
2. To find the associated resource, go to
http://www.freescale.com
and perform a search using this term with the “x”
replaced by the revision of the device you are using.
Figure 1
shows the functional modules in the chip.
2
Freescale Semiconductor, Inc.
Kinetis KL24 Sub-Family, Rev5 08/2014.
Kinetis KL24 Family
ARM Cortex-M0+
Core
Debug
interfaces
Interrupt
controller
System
Internal
watchdog
Memories and
Memory Interfaces
Program
flash
Clocks
Phase-
locked loop
Frequency-
locked loop
DMA
RAM
BME
MTB
Low/high
frequency
oscillator
Internal
reference
clocks
and Integrity
Internal
watchdog
Security
Analog
12-bit ADC
x1
Timers
Timers
1x6ch+2x2ch
Low
power timer
x1
Communication
Interfaces
I
C
x2
Low power
UART
x1
SPI
x2
UART
x2
USB LS/FS
x1
2
Human-Machine
Interface (HMI)
GPIOs
with
interrupt
Analog
comparator
x1
6-bit DAC
Periodic
interrupt
timers
RTC
LEGEND
Migration difference from KL14 family
Figure 1. Functional block diagram
Kinetis KL24 Sub-Family, Rev5 08/2014.
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 16
2.2.7 Designing with radiated emissions in mind..........17
2.2.8 Capacitance attributes.........................................17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications..................................17
2.3.2 General switching specifications......................... 18
2.4 Thermal specifications..................................................... 18
2.4.1 Thermal operating requirements......................... 18
2.4.2 Thermal attributes................................................19
3 Peripheral operating requirements and behaviors.................. 19
3.1 Core modules.................................................................. 19
3.1.1 SWD electricals .................................................. 19
3.2 System modules.............................................................. 21
3.3 Clock modules................................................................. 21
3.3.1 MCG specifications..............................................21
3.3.2 Oscillator electrical specifications........................23
3.4 Memories and memory interfaces................................... 25
3.4.1 Flash electrical specifications.............................. 25
3.5 Security and integrity modules........................................ 27
3.6 Analog............................................................................. 27
3.6.1 ADC electrical specifications............................... 27
3.6.2 CMP and 6-bit DAC electrical specifications....... 30
3.7 Timers..............................................................................32
3.8 Communication interfaces............................................... 32
3.8.1 USB electrical specifications............................... 32
3.8.2 USB VREG electrical specifications.................... 32
3.8.3 SPI switching specifications................................ 33
3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 37
3.8.5 UART...................................................................39
Dimensions............................................................................. 39
4.1 Obtaining package dimensions....................................... 39
Pinout...................................................................................... 39
5.1 KL24 Signal Multiplexing and Pin Assignments...............39
5.2 KL24 pinouts....................................................................42
Ordering parts......................................................................... 46
6.1 Determining valid orderable parts....................................46
Part identification.....................................................................46
7.1 Description.......................................................................47
7.2 Format............................................................................. 47
7.3 Fields............................................................................... 47
7.4 Example...........................................................................47
Terminology and guidelines.................................................... 48
8.1 Definition: Operating requirement....................................48
8.2 Definition: Operating behavior......................................... 48
8.3 Definition: Attribute.......................................................... 48
8.4 Definition: Rating............................................................. 49
8.5 Result of exceeding a rating............................................ 49
8.6 Relationship between ratings and operating
requirements....................................................................50
8.7 Guidelines for ratings and operating requirements..........50
8.8 Definition: Typical value...................................................51
8.9 Typical value conditions.................................................. 52
9 Revision history.......................................................................52
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Freescale Semiconductor, Inc.
Kinetis KL24 Sub-Family, Rev5 08/2014.
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
T
STG
T
SDR
Description
Storage temperature
Solder temperature, lead-free
Min.
–55
—
Max.
150
260
Unit
°C
°C
Notes
1
2
1. Determined according to JEDEC Standard JESD22-A103,
High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
MSL
Description
Moisture sensitivity level
Min.
—
Max.
3
Unit
—
Notes
1
1. Determined according to IPC/JEDEC Standard J-STD-020,
Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
V
HBM
V
CDM
I
LAT
Description
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device
model
Latch-up current at ambient temperature of 105 °C
Min.
–2000
–500
–100
Max.
+2000
+500
+100
Unit
V
V
mA
Notes
1
2
3
1. Determined according to JEDEC Standard JESD22-A114,
Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101,
Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78,
IC Latch-Up Test.
Kinetis KL24 Sub-Family, Rev5 08/2014.
5
Freescale Semiconductor, Inc.
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