4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
4Mb
ZBT
®
SRAM
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High frequency and 100 percent bus utilization
Fast cycle times: 10ns, 11ns, and 12ns
Single +3.3V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control
signal interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or interleaved burst modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 8Mb, and
16Mb ZBT SRAM family
165-pin FBGA package
100-pin TSOP package
Automatic power-down
MT55L256L18F1, MT55L128L32F1,
MT55L128L36F1; MT55L256V18F1,
MT55L128V32F1, MT55L128V36F1
3.3V V
DD
, 3.3V or 2.5V I/O
100-Pin TQFP
1
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz)
7.5ns/10ns/100 MHz
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Package
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example:
MARKING
-10
-11
-12
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
MT55L256L18F1
MT55L128L32F1
MT55L128L36F1
MT55L256V18F1
MT55L128V32F1
MT55L128V36F1
T
F*
None
IT
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
GENERAL DESCRIPTION
The Micron
®
Zero Bus Turnaround
™
(ZBT
®
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,
128K x 32, or 128K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles when
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
MT55L256L18F1T-12
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_E.p65 – Rev. 2/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 18
18
SA0, SA1, SA
MODE
CLK
CKE#
K
CE
ADDRESS
REGISTER
18
SA1
D1
SA0
D0
ADV/LD#
K
16
Q1 SA1'
SA0'
BURST Q0
LOGIC
18
18
18
WRITE ADDRESS
REGISTER
ADV/LD#
BWa#
BWb#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
18
256K x 9 x 2
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
18
DQs
OE#
CE#
CE2
CE2#
READ LOGIC
INPUT E
REGISTER
18
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
17
SA0, SA1, SA
MODE
CLK
CKE#
K
CE
ADDRESS
REGISTER
17
SA1
D1
SA0
D0
ADV/LD#
K
15
Q1 SA1'
SA0'
Q0
17
17
O
U
T
P
U
T
B
U
F
F
E
R
S
E
17
BURST
LOGIC
WRITE ADDRESS
REGISTER
ADV/LD#
BWa#
BWb#
BWc#
BWd#
R/W#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
36
128K x 8 x 4
(x32)
WRITE
DRIVERS
128K x 9 x 4
(x36)
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
36
DQs
OE#
CE#
CE2
CE2#
INPUT
E
REGISTER
36
READ LOGIC
NOTE:
Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions and timing diagrams
for detailed information.
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_E.p65 – Rev. 2/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
GENERAL DESCRIPTION (continued)
The synchronous inputs include all addresses, all
data inputs, chip enable (CE#), two additional chip
enables for easy depth expansion (CE2, CE2#), cycle
start input (ADV/LD#), synchronous clock enable
(CKE#), byte write enables (BWa#, BWb#, BWc#, and
BWd#) and read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The flow-through data-
out (Q) is enabled by OE#. WRITE cycles can be from
one to four bytes wide as controlled by the write control
inputs.
All READ, WRITE and DESELECT cycles are initiated
by the ADV/LD# input. Subsequent burst addresses can
be internally generated as controlled by the burst
advance pin (ADV/LD#). Use of burst mode is optional.
It is allowable to give an address for each individual
READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock cycle
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The write data associated with the address is
required one cycle later, or on the rising edge of clock
cycle two.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa#
controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; and BWd# controls DQd pins. Cycle
types can only be defined when an address is loaded,
i.e., when ADV/LD# is LOW. Parity/ECC bits are only
available on the x18 and x36 versions.
Micron’s 4Mb ZBT SRAMs operate from a +3.3V V
DD
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requiring
high bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_E.p65 – Rev. 2/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
NC
NC
NC
x32
NC
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
SS
V
DD
V
DD
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
x36
DQc
DQc
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32
x36
V
SS
V
DD
Q
NC
DQd DQd
NC
DQd DQd
NC
NC
DQd
MODE (LBO#)
SA
SA
SA
SA
SA1
SA0
DNU
DNU
V
SS
V
DD
DNU
DNU
SA
SA
SA
SA
SA
SA
SA
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32
NC
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
ZZ
V
DD
V
SS
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
x36
DQa
DQa
DQa
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
x32
x36
V
SS
V
DD
Q
DQb DQb
DQb DQb
NC
DQb
SA
SA
NF*
NF*
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc# BWc#
BWd# BWd#
CE2
CE#
SA
SA
NC
NC
SA
NC
NC
DQb
DQb
DQc
DQc
DQc
DQc
NC
NC
DQa
DQa
DQb
DQb
DQc
DQc
DQb
DQb
DQd
DQd
DQa
DQa
DQb
DQb
NC
NC
DQb
DQb
DQb
NC
DQd
DQd
DQd
DQd
DQa
DQa
DQa
NC
DQb
DQb
DQb
DQb
* Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_E.p65 – Rev. 2/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
PIN ASSIGNMENT (Top View)
100-Pin TQFP
SA
NC
NC
V
DD
Q
V
SS
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
V
SS
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/DQb*
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
SS
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NC/DQa*
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
DD
V
DD
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
NC
V
SS
V
DD
Q
NC
NC
NC
x32/x36
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_E.p65 – Rev. 2/02
NC/DQc*
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
SS
V
DD
V
DD
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NC/DQd*
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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