ADVANCE
‡
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
18Mb QDR™ SRAM
2-Word Burst
FEATURES
• 18Mb Density
• Separate independent read and write data ports with
concurrent transactions
• 100% bus utilization DDR READ and WRITE
operation
• High frequency operation with future migration to
higher clock frequencies
• Fast clock to valid data times
• Full data coherency, providing most current data
• Two-tick burst counter for low DDR transaction size
• Double data rate operation on read and write ports
• Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
• Single address bus
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• +2.5V core and HSTL I/O
• Clock-stop capability
• 13x15mm, 1mm pitch, 11 x 15 grid FBGA package
• User programmable impedence output
• JTAG boundary scan
MT54V1MH18A
MT54V512H36A
165-BALL FBGA
GENERAL DESCRIPTION
The Micron
®
QDR™ (Quad Data Rate™) Synchro-
nous Pipelined Burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS pro-
cess. The QDR architecture consists of two separate DDR
(double data rate) ports to access the memory array. The
read port has dedicated data outputs to support READ
operations. The write port has dedicated data inputs to
support WRITE operations. This architecture eliminates
the need for high-speed bus turnaround. Access to each
port is accomplished using a common address bus. Ad-
dresses for reads and writes are latched on rising edges of
the K and K# input clocks, respectively. Each address
location is associated with two words that burst sequen-
tially into or out of the device. Since data can be trans-
ferred into
and
out of the device on every rising edge of
both clocks (K, and K#, C and C#) memory bandwidth is
maximized while simplifying system design by eliminat-
ing bus turnarounds.
Depth expansion is accomplished with port selects
for each port (read R#, write W#) which are received at K
rising edge. Port selects permit independent port opera-
tion. All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active LOW
byte writes (BW0#, BW1#) permit byte write selection.
Write data and byte writes are registered on the rising
edges of both K and K#. The addressing within each burst
of two is fixed and sequential, beginning with the lowest
OPTIONS
• Clock Cycle Timing
6ns (167 MHz)
7.5ns (133 MHz)
10ns (100 MHz)
• Configurations
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
MARKING*
-6
-7.5
-10
MT54W1MH18A
MT54W512H36A
F
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/numberguide.
VALID PART NUMBERS
PART NUMBER
MT54V1MH18AF-xx
MT54V512H36AF-xx
DESCRIPTION
1 Meg x 18, QDRb2 FBGA
512K x 36, QDRb2 FBGA
18M 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_3.p65 – Rev. 3, Pub. 5/02
1
©2002, Micron Technology, Inc.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
GENERAL DESCRIPTION (continued)
and ending with the highest address. All synchronous
data outputs pass through output registers controlled by
the rising edges of the output clocks (C and C# if pro-
vided, otherwise K and K#).
Four balls are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test clock
(TCK) and test data-out (TDO). JTAG circuitry is used to
serially shift data to and from the SRAM. JTAG inputs use
JEDEC-standard 2.5V I/O levels to shift data during this
testing mode of operation.
The SRAM operates from a +2.5V power supply, and
all inputs and outputs are HSTL-compatible. The device
is ideally suited for applications that benefit from a high-
speed fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds)
for the latest data sheet.
HIGH. If C and C# are tied HIGH, they may not be toggled
during device operation. Output tri-stating is automati-
cally controlled such that the bus is released if no data is
being delivered. This permits banked SRAM systems with
no complex OE timing generation. Back-to-back READ
cycles are initiated every K rising edge.
WRITE cycles are initiated by W# LOW at K rising
edge. The address for the WRITE cycle is provided at the
following K# rising edge. Data is expected at the rising
edge of K and K# beginning at the same K which initiated
the cycle. Write registers are incorporated to facilitate
pipelined self-timed WRITE cycles and provide fully co-
herent data for all combinations of READs and WRITEs. A
READ can immediately follow a WRITE even if they are to
the same address. Although the WRITE data has not been
written to the memory array, the SRAM will deliver the
data from the Write Register instead of using the older
data from the memory array. The latest data is always
utilized for all bus transactions. WRITE cycles can be
initiated on every K rising edge.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable
burst of two data, requiring one full clock cycle of bus
utilization.The resulting benefit is that short data trans-
actions can remain in operation on both buses provided
that the address rate can be maintained by the system (2x
the clock frequency).
READ cycles are pipelined. The request is initiated by
asserting R# LOW at K rising edge. Data is delivered after
the next rising edge of K using C and C# as the output
timing references, or using K and K# if C and C# are tied
BYTE WRITE OPERATIONS
BYTE WRITE operations are supported. The active
LOW byte write controls are registered coincident with
their corresponding data. This feature can eliminate the
need for some READ/MODIFY/WRITE cycles, collapsing
it to a single BYTE WRITE operation in some instances.
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
n
ADDRESS
R#
W#
K
K#
n
ADDRESS
REGISTRY
& LOGIC
W#
BW0#
BW1#
D (Data In)
R#
K
K#
18
DATA
REGISTRY
& LOGIC
36
WR
R E
I G
T
E 2
WD
R R
I I
T V
E E
R
2
n
x 36
MEMORY
ARRAY
S
E A
NM
S P
E S
36
MUX
RO
E U
G T
P
AU
T
C
C, C#
or
K, K#
36
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
B
U
F
F
E
R
18
Q
(Data Out)
2
K
CQ, CQ#
(Echo Clock Out)
NOTE:
1. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing
diagrams for detailed information.
2. n = 19
18M 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_3.p65 – Rev. 3, Pub. 5/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
The QDR SRAM is equipped with programmable im-
pedance output buffers. This allows a user to match the
driver impedance to the system. To adjust the imped-
ance, an external precision resistor (RQ) is connected
between the ZQ ball and V
SS
. The value of the resistor
must be five times the desired impedance. For example,
a 350W resistor is required for an output impedance of
70W. To ensure that output impedance is one fifth the
value of RQ (within 15 percent), the range of RQ is 175W
to 350W. Alternately, the ZQ ball can be connected di-
rectly to V
DD
Q, which will place the device in a minimum
impedance mode.
Output impedance updates may be required because
variations may occur in supply voltage and temperature
over time. The device samples the value of RQ. An update
of the impedance is transparent to the system. Imped-
ance updates do not affect device operation, and all data
sheet timing and current specifications are met during
an update.
The device will power up with an output impedance
set at 50W. To guarantee optimum output driver imped-
ance after power-up, the SRAM needs 1,024 cycles to
update the impedance. The user can operate the part
with fewer than 1,024 clock cycles, but optimal output
impedance is not guaranteed.
CLOCK CONSIDERATIONS
The device does not utilize internal phase-locked loops
and can therefore be placed into a stopped-clock state to
minimize power without lengthy restart times. It is
strongly recommended that the clocks operate for a num-
ber of cycles prior to initiating commands to the SRAM.
This delay permits transmission line charging effects to
be overcome and allows the clock timing to be nearer to
its steady-state value.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock pair
by tying C and C# HIGH. In this mode the SRAM will use
K and K# in place of C and C#. This mode provides the
most rapid data output but does not compensate for
system clock skew and flight times.
DEPTH EXPANSION
Port select inputs are provided for the read and
write ports. This allows for easy depth expansion. Both
Port Selects are sampled on the rising edge of K only.
Each port can be independently selected and deselected
and do not affect the operation of the opposite port.
All pending transactions are completed prior to a port
deselecting.
APPLICATION EXAMPLE
SRAM #1
Vt
R
D
SA
B
W
R W n
# # #
ZQ
Q
C C#
K
K#
R = 250Ω
D
SA
SRAM #4
B
W
R W n
# # #
ZQ
Q
C C# K K#
R = 250Ω
DATA IN
DATA OUT
Addresses
Read#
BUS
Write#
MASTER
BWn#
R
Vt
Vt
(CPU
or
ASIC)
Return CLK
Source CLK
Return CLK#
Source CLK#
Vt
Vt
R = 50Ω Vt = V
REF
18M 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_3.p65 – Rev. 3, Pub. 5/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
1 MEG x 18 BALL ASSIGNMENT (TOP VIEW)
165-BALL FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
CQ#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA*
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
SA
4
W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
BW1#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC
BW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
V
SS
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
*Expansion addresses: 3A for 36Mb.
512K x 36 BALL ASSIGNMENT (TOP VIEW)
165-BALL FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
CQ#
Q27
D27
D28
Q29
Q30
D30
NC
D31
Q32
Q33
D33
D34
Q35
TDO
2
V
SS
Q18
Q28
D20
D29
Q21
D22
V
REF
Q31
D32
Q24
Q34
D26
D35
TCK
3
NC
D18
D19
Q19
Q20
D21
Q22
V
DD
Q
D23
Q23
D24
D25
Q25
Q26
SA
4
W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
BW2#
BW3#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
BW1#
BW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
V
SS
/SA*
D17
D16
Q16
Q15
D14
Q13
V
DD
Q
D12
Q12
D11
D10
Q10
Q9
SA
10
V
SS
Q17
Q7
D15
D6
Q14
D13
V
REF
Q4
D3
Q11
Q1
D9
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
*Expansion addresses: 9A for 36Mb.
NOTE:
BW0# controls writes to D0:D8. BW1# controls writes to D9:D17. BW2# controls writes to D18:D26. BW3# controls
writes to D27:D35.
18M 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_3.p65 – Rev. 3, Pub. 5/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
1 MEG x 18, 512K x 36
2.5V V
DD
, HSTL, QDRb2 SRAM
FBGA BALL DESCRIPTIONS
SYMBOL
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of K. Balls 9A and 3A are reserved for the next higher-
order address inputs on the 36Mb device. All transactions operate on a burst of four
words (two clock periods of bus activity). These inputs are ignored when both ports are
deselected.
Synchronous Read: When LOW this input causes the address inputs to be registered and a
READ cycle to be initiated. This input must meet setup and hold times around the rising
edge of K and is ignored on the subsequent rising edge of K.
Synchronous Write: When LOW this input causes the address inputs to be registered and a
WRITE cycle to be initiated. This input must meet setup and hold times around the rising
edge of K and is ignored on the subsequent rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective byte to be
registered and written if W# had initiated a WRITE cycle. These signals must meet setup
and hold times around the rising edges of K and K# for each of the two rising edges
comprising the WRITE cycle. See Ball Assignment figures for signal to data relationships.
Input Clock: This input clock pair registers address and control inputs on the rising edge
of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180
degrees out of phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of tuning device output
data. The rising edge of C is used as the output timing reference for second and fourth
output data. The rising edge of C# is used as the output reference for first and third
output data. Ideally, C# is 180 degrees out of phase with C. C and C# may be tied HIGH to
force the use of K and K# as the output reference clocks instead of having to provide C
and C# clocks. If tied HIGH, these inputs may not be allowed to toggle during device
operation.
IEEE 1149.1 Test Inputs: 2.5V I/O levels. These balls may be left Not Connected if the JTAG
function is not used in the circuit.
IEEE 1149.1 Clock Input: 2.5V I/O levels. This ball must be tied to V
SS
if the JTAG function is
not used in the circuit.
HSTL Input Reference Voltage: Nominally V
DD
Q/2 but may be adjusted to improve system
noise margin. Provides a reference voltage for the HSTL input buffer trip point.
Output Impedance Matching Input: This input is used to tune the device outputs to the
system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a
resistor from this ball to ground. Alternately, this ball can be connected directly to V
DD
Q,
which enables the minimum impedance mode. This ball cannot be connected directly to
GND or left unconnected.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising
edges of K and K# during WRITE operations. See ball assignment figures for ball site
location of individual signals. The x18 device uses D0–D17. Remaining signals are NC. The
x36 device uses D0–D35.
Synchronous Echo Clock Outputs. The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as data valid indication. These signals run
freely and do not stop when Q tristates.
(continued on next page)
R#
Input
W#
Input
BW_#
Input
K
K#
Input
C
C#
Input
TMS
TDI
TCK
V
REF
ZQ
Input
Input
Input
Input
D_
Input
CQ#, CQ
Output
18M 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V1MH18A_3.p65 – Rev. 3, Pub. 5/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
