L7C108
L7C109
128K x 8 Static RAM
FEATURES
128K x 8 Static RAM with Chip
Select Powerdown, Output Enable
and Single or Dual Chip Selects
High Speed — to 15 ns maximum
Operational Power, -L Version
Active: 140 mA at 15 ns
Standby: 1 mA max
Data Retention at 2 V for Battery
Backup Operation
Screened to MIL-STD-883, Class B
or to SMD 5962-89598
Package Styles Available:
Pin Configuration
32-pin Ceramic DIP
32-pin Ceramic SOJ
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
32-pin Quad CLCC
A
2
A
1
A
0
NC
V
CC
A
16
NC
32-pin Ceramic LCC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
DQ
2
DQ
3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
4
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
1
5
6
7
8
9
10
11
12
13
Top
View
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
DQ
8
14 15 16 17 18 19 20
OVERVIEW
The L7C108 and L7C109 are high-perfor-
mance, low-power CMOS static RAMs.
The storage circuitry is organized as
131,072 words by 8 bits per word. The
8 Data In and Data Out signals share I/O
pins. The L7C108 has a single active-
low Chip Enable. The L7C109 has two
devices are available in three speeds
with maximum access times from 15 ns
to 45 ns.
Inputs and outputs are TTL compatible.
Operation is from a single +5 V power
supply. Power consumption is 140 mA
retained in inactive storage with a supply
voltage as low as 2 V.
The L7C108 and L7C109 provide asyn-
matching access and cycle times. The
Chip Enables and a three-state I/O bus
with a separate Output Enable control
simplify the connection of several chips
for increased storage capacity.
Memory locations are specified on
address pins A
0
through A
16
. For the
L7C108, reading from a designated
location is accomplished by present-
ing an address and driving CE
1
and OE
LOW while WE remains HIGH. For the
L7C109, CE
1
and OE must be LOW
while CE
2
and WE are HIGH.The data in
the addressed memory location will then
appear on the Data Out pins within one
access time. The output pins stay in a
high-impedance state when CE
1
or OE is
HIGH, or CE
2
Writing to an addressed location is
accomplished when the active-low CE
1
and WE inputs are both LOW, and CE
2
may be used to terminate the write oper-
ation. Data In and Data Out signals have
the same polarity.
Latchup and static discharge protection
are provided on-chip. The L7C108 and
L7C109 can withstand an injection cur-
rent of up to 200 mA on any pin without
damage.
DQ
2
DQ
3
V
SS
DQ
4
DQ
5
DQ
6
DQ
7
LOGIC Devices Incorporated
www.logicdevices.com
1
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
L7C108
L7C109
128K x 8 Static RAM
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2)
Storage temperature…………………………………………...….……............……-65°C to +150°C
Operating ambient temperature………………………………………......….......…-55°C to +125°C
Vcc supply voltage with respect to ground…………….…………………….......….-0.5 V to +7.0 V
Input signal with respect to ground.………………………….………………..…..…-3.0 V to +7.0 V
Signal applied to high impedance output……………………………………........…-3.0 V to +7.0 V
Output current into low outputs………………………………………….…......................……25 mA
Latchup current….........................……………..…………………………...……................ >200 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active, Operation, Military
Data Retention, Military
Temperature Range (Ambient)
-55°C to +125°C
-55°C to +125°C
Supply Voltage
4.5 V
2.0 V
V
CC
V
CC
5.5 V
5.5 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 5)
L7C108/109
Symbol Parameter
V
OH
V
OL
V
IH
Output High Voltage
Output Low Voltage
Input High Voltage
L7C108/109-L
Min
2.4
Test Condition
V
CC
= 4.5V,
I
OH
= -4 mA
I
OL
= 8 mA
Min
2.4
Max
0.4
Max
Unit
V
V
V
0.4
2.2
Vcc
+0.3
-3.0
-10
-10
0.8
+10
+10
25
5
0.75
8
8
2.2
Vcc
+0.5
V
IL
I
Ix
I
OZ
I
CC2
I
CC3
I
CC4
C
IN
C
OUT
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
Current, TTL Standby
V
CC
Current,
CMOS
Standby
V
CC
Current, Data Retention
Input Capacitance
Output Capacitance
V
CC
=
Ambient Temp = 25°C,
V
CC
= 5 V
GND
< V
IN
< V
CC
-0.5
-10
-10
0.8
+10
+10
25
10
-
8
8
V
μA
μA
mA
mA
mA
pF
pF
L7C108/109
Symbol Parameter
I
CC1
V
CC
Current, Active
L7C108/109-L
45
15
20
25
35
45 Unit
mA
Test Condition
15
140
20
25
35
140 140 135 125
140 140
140 130 125
LOGIC Devices Incorporated
www.logicdevices.com
3
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
R
EAD
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L
Symbol Parameter
t
AVAV
t
t
t
t
t
t
t
t
t
PU
0
Output Enable Low to Output Valid
0
6
0
3
7
8
0
6
0
Address Change to Output Change
3
15
3
8
10
0
10
0
Read Cycle Time
15
15
3
20
3
10
10
0
15
0
20
20
3
25
3
15
15
0
20
25
25
3
35
3
20
20
35/35-L 45/45-L
35
35
3
45
45
45
Min Max Min Max Min Max Min Max Min Max
R
EAD
C
YCLE
- A
DDRESS
C
ONTROLLED
Notes 13, 14
t
AVAV
ADDRESS
t
AVQV
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
AVQX
t
PU
I
CC
t
PD
R
EAD
C
YCLE
- CE/OE C
ONTROLLED
N
OTES
13, 15
CE
t
AVAV
t
ELQV
t
ELQX
t
EHQZ
OE
t
GLQX
DATA OUT
HIGH IMPEDANCE
t
GLQV
DATA VALID
t
GHQZ
HIGH
IMPEDANCE
t
PU
Icc
50%
t
PD
50%
LOGIC Devices Incorporated
www.logicdevices.com
4
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS
Over Operating Range
R
EAD
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Symbol
t
PD
t
CDR
0
Parameter
Min Max Min Max Min Max Min Max Min Max
15
0
20
0
25
0
35
0
45
D
ATA
R
ETENTION
Notes 9, 10
DATA RETENTION MODE
V
CC
t
CDR
CE
4.5 V
4.5 V
≥2V
t
PD
V
IH
V
IH
W
RITE
C
YCLE
Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
15/15-L 20/20-L 25/25-L 35/35-L 45/45-L
Symbol
t
AVAV
t
ELWH
t
AVWL
t
AVWH
t
WHAX
t
WLWH
t
DVWH
t
WHDX
t
t
Parameter
Write Cycle Time
Chip Enable Low to End of Write Cycle
Address Valid to Beginning of Write Cycle
Address Setup to End of Write Cycle
Address Hold After End Of Write
Write Enable Pulse Width Low
Data Setup to End of Write Cycle
Data Hold to End of Write
Min Max Min Max Min Max Min Max Min Max
15
12
0
15
0
12
7
0
5
7
20
12
0
17
0
15
10
0
5
8
25
20
0
20
0
20
12
0
5
10
35
25
0
25
0
30
20
0
5
25
45
35
0
35
0
40
20
0
5
30
LOGIC Devices Incorporated
www.logicdevices.com
5
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
