BGA7350
50 MHz to 250 MHz high linearity Si variable gain amplifier;
24 dB gain range
Rev. 1 — 21 December 2011
Product data sheet
1. Product profile
1.1 General description
The BGA7350 MMIC is a dual independently digitally controlled IF Variable Gain
Amplifier (VGA) operating from 50 MHz to 250 MHz. Each IF VGA amplifies with a gain
range of 24 dB and at its maximum gain setting delivers 17 dBm output power at 1 dB gain
compression and a superior linear performance.
The BGA7350 Dual IF VGA is optimized for a differential gain error of less than
0.1
dB
for accurate gain control and has a total integrated gain error of less than
0.4
dB.
The gain controls of each amplifier are separate digital gain-control word, which is
provided externally through two sets of 5 bits.
The BGA7350 is housed in a 32 pins 5 mm
5 mm leadless HVQFN32 package.
1.2 Features and benefits
Dual independent digitally controlled 24 dB gain range VGAs, with 5-bit control
interface
50 MHz to 250 MHz frequency operating range
Gain step size: 1 dB
0.1 dB
18.5 dB power gain
Fast gain stage switching capability
17 dBm output power at 1 dB gain compression
5 V single supply operation with power-down control
Logic-level shutdown control pin reduces supply current
Excellent ESD protection at all pins
Moisture sensitivity level 2
Unconditionally stable
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
Compatible with W-CDMA / WiMAX / LTE base-station infrastructure / multi carrier
systems
Multi channel receivers
General use for ADC driver applications
NXP Semiconductors
BGA7350
50 MHz to 250 MHz high linearity Si variable gain amplifier
1.4 Quick reference data
Table 1.
Quick reference data
A_EN = "1"; B_EN = "1" (VGA enabled). Typical values at V
CC
= 5 V; I
CC
= 245 mA;
Tuned for f
IF
= 172 MHz; B = 28 MHz; T
case
= 25
C; Differential input resistance matched to 140
;
Differential output resistance matched to 200
; unless otherwise specified; see
Section 11
“Application information”.
Symbol
V
CC
I
CC
Parameter
supply voltage
supply current
Conditions
V
CC(A)
+ V
CC(B)
I
CC(A)
+ I
CC(B)
A_EN = "0"; B_EN = "0"
A_EN = "1"; B_EN = "1"
G
p
R
i(dif)
R
o(dif)
NF
IP3
O
P
L(1dB)
E
G(dif)
E
(dif)
power gain
differential input
resistance
differential output
resistance
noise figure
output third-order
intercept point
output power at 1 dB
gain compression
differential gain error
differential phase error
upper 12 dB gain range
per gain step (for all
consecutive gain steps)
[1]
[2]
Maximum gain; gain code = 00000.
Minimum gain; gain code = 11000.
Min
Typ
Max Unit
5.25 V
5
280
mA
mA
dB
dB
dB
dBm
dBm
dB
deg
deg
4.75 5
-
-
[1]
[2]
3
245
maximum gain
minimum gain
17.5 18.5 19.5 dB
7
100
160
5.5 4
140
200
6
0.8
43
17
180
240
8
1
-
-
maximum gain
increased rate per gain step
upper 5 gain steps
upper 5 gain steps
[1]
-
-
-
-
-
-
-
[1]
[1]
0.1 -
1.5
0.5
-
-
BGA7350
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 December 2011
2 of 31
NXP Semiconductors
BGA7350
50 MHz to 250 MHz high linearity Si variable gain amplifier
2. Pinning information
2.1 Pinning
25 A_OUT_N
24 A_OUT_P
23 A_OUT_N
22 A_EN
21 GNDA
20 GNDB
19 B_EN
18 B_OUT_N
17 B_OUT_P
B_D0 10
B_IN_P 11
B_IN_N 12
GNDB 13
V
CCB
14
B_OUT_P 15
B_OUT_N 16
9
aaa-001223
terminal 1
index area
A_D2
A_D3
A_D4
n.c.
n.c.
B_D4
B_D3
B_D2
1
2
3
4
5
6
7
8
BGA7350
B_D1
Transparent top view
Fig 1.
Pin configuration SOT617-1
2.2 Pin description
Table 2.
Symbol
A_D2
A_D3
A_D4
n.c.
n.c.
B_D4
B_D3
B_D2
B_D1
B_D0
B_IN_P
B_IN_N
GNDB
V
CCB
B_OUT_P
B_OUT_N
B_EN
GNDA
BGA7350
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13, 20
14
15, 17
16, 18
19
21, 28
Description
MSB
2 for gain control interface of channel A
MSB
1 for gain control interface of channel A
MSB for gain control interface of channel A
not connected
[1]
not connected
[1]
MSB for gain control interface of channel B
MSB
1 for gain control interface of channel B
MSB
2 for gain control interface of channel B
LSB + 1 for gain control interface of channel B
LSB for gain control interface of channel B
channel B positive input
[2]
channel B negative input
[2]
ground for channel B
supply voltage for channel B
channel B positive output
[2]
channel B negative output
[2]
power enable pin for channel B
ground for channel A
© NXP B.V. 2011. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 1 — 21 December 2011
26 A_OUT_P
29 A_IN_N
30 A_IN_P
28 GNDA
32 A_D1
31 A_D0
27 V
CCA
3 of 31
NXP Semiconductors
BGA7350
50 MHz to 250 MHz high linearity Si variable gain amplifier
Pin description
…continued
Pin
22
23, 25
24, 26
27
29
30
31
32
GND paddle
Description
power enable pin for channel A
channel A negative output
[2]
channel A positive output
[2]
supply voltage for channel A
channel A negative input
[2]
channel A positive input
[2]
LSB for gain control interface of channel A
LSB + 1 for gain control interface of channel A
RF ground and DC ground
[3]
Table 2.
Symbol
A_EN
A_OUT_N
A_OUT_P
V
CCA
A_IN_N
A_IN_P
A_D0
A_D1
GND
[1]
[2]
[3]
Pin to be left open.
Each channel should be independently enabled with logic HIGH and disabled with logic LOW.
The center metal base of the SOT617-1 also functions as heatsink for the VGA.
3. Ordering information
Table 3.
Ordering information
Package
Name
BGA7350
Description
Version
SOT617-1
HVQFN32 plastic thermal enhanced very thin quad flat package;
no leads; 32 terminals; body 5
5
0.85 mm
Type number
BGA7350
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 December 2011
4 of 31
NXP Semiconductors
BGA7350
50 MHz to 250 MHz high linearity Si variable gain amplifier
4. Functional diagram
A_OUT_N
A_OUT_P
A_OUT_N
OUT-
V
DD
V
EE
A_EN
GNDA
GAIN
CONTROL
GNDB
B_EN
V
CC
B_OUT_N
B_OUT_P
aaa-001224
A_D3
A_D4
A_VCOM
GAIN
CONTROL
IN+
CM
IN-
V
CC
REGULATOR
V
EE
GAIN
CONTROL
A_D2
V
DD
V
CC
BGA7350
V
CC
V
DD
REGULATOR
V
EE
B_VCOM
IN-
CM
IN+
B_D4
B_D3
B_D2
GAIN
CONTROL
V
EE
V
DD
OUT-
OUT+
B_IN_P
EN
EN
OUT+
A_OUT_P
B_IN_N
V
CCB
A_OUT_P
A_IN_N
A_IN_P
GNDA
A_D1
A_D0
V
CCA
Fig 2.
Functional diagram
5. Enable control
Table 4.
Mode
Enable / disable control settings
Function description
Mode description Enable
Disable
"0"
"1"
"0"
"1"
V
EN
(V)
0
1.6
0.8
I
en
(A)
-
1
1
A_EN B_EN Min Max Min Max
A_EN, B_EN VGA function off
A_EN, B_EN VGA in operating mode Enable
5.25 -
BGA7350
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 21 December 2011
B_OUT_N
B_D0
GNDB
B_D1
5 of 31
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