Freescale Semiconductor
Addendum
Document Number: QFN_Addendum
Rev. 0, 07/2014
Addendum for New QFN
Package Migration
This addendum provides the changes to the 98A case outline numbers for products covered in this book.
Case outlines were changed because of the migration from gold wire to copper wire in some packages. See
the table below for the old (gold wire) package versus the new (copper wire) package.
To view the new drawing, go to Freescale.com and search on the new 98A package number for your
device.
For more information about QFN package use, see EB806:
Electrical Connection Recommendations for
the Exposed Pad on QFN and DFN Packages.
© Freescale Semiconductor, Inc., 2014. All rights reserved.
Part Number
MC68HC908JW32
MC9S08AC16
MC9S908AC60
MC9S08AC128
MC9S08AW60
MC9S08GB60A
MC9S08GT16A
MC9S08JM16
MC9S08JM60
MC9S08LL16
MC9S08QE128
MC9S08QE32
MC9S08RG60
MCF51CN128
MC9RS08LA8
MC9S08GT16A
MC9S908QE32
MC9S908QE8
MC9S08JS16
MC9S08QB8
MC9S08QG8
MC9S08SH8
MC9RS08KB12
MC9S08QG8
MC9RS08KB12
MC9S08QG8
MC9RS08KA2
6 DFN
Package Description
48 QFN
Original (gold wire)
Current (copper wire)
package document number package document number
98ARH99048A
98ASA00466D
48 QFN
32 QFN
32 QFN
32 QFN
24 QFN
98ARL10606D
98ARH99035A
98ARE10566D
98ASA00071D
98ARL10608D
98ASA00466D
98ASA00473D
98ASA00473D
98ASA00736D
98ASA00734D
24 QFN
24 QFN
24 QFN
16 QFN
8 DFN
98ARL10605D
98ARE10714D
98ASA00087D
98ARE10614D
98ARL10557D
98ASA00474D
98ASA00474D
98ASA00602D
98ASA00671D
98ASA00672D
98ARL10602D
98ASA00735D
Addendum for New QFN Package Migration, Rev. 0
2
Freescale Semiconductor
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF51CN128
Rev. 4, 5/2009
MCF51CN128
MCF51CN128 ColdFire
Microcontroller
Cover: MCF51CN128
The MCF51CN128 device is a low-cost, low-power,
high-performance 32-bit ColdFire V1 microcontroller (MCU)
featuring 10/100 BASE-T/TX fast ethernet controller (FEC),
media independent interface (MII) to connect an external
physical transceiver (PHY), and multi-function external bus
interface.
MCF51CN128 also has multiple communication interfaces
for various ethernet gateway applications. MCF51CN128 is
the first ColdFire V1 device to incorporate ethernet and
external bus interface along with new features to minimize
power consumption and increase functionality in low-power
modes.
The MCF51CN128 features the following functional units:
• 32-bit ColdFire V1 Central Processing Unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up
to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz
CPU from 2.1 V to 1.8 V across temperature range of
–40 °C to 85 °C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz
performance when running from internal RAM
(0.76 DMIPS/MHz from flash)
– ColdFire Instruction Set Revision C (ISA_C)
– Support for up to 45 peripheral interrupt requests and 7
software interrupts
• On-Chip Memory
– 128 KB Flash, 24 KB RAM
– Flash read/program/erase over full operating voltage
and temperature
– On-chip memory aliased to create a contiguous memory
space with off-chip memory
– Security circuitry to prevent unauthorized access to
Peripherals, RAM, and flash contents
• Ethernet
– FEC—10/100 BASE-T/TX, bus-mastering fast ethernet
controller with direct memory access (DMA); supports
half or full duplex; operation is limited to 3.0 V to 3.6 V
80 LQFP
14 mm
×
14 mm
64 LQFP
10 mm
×
10 mm
48 QFN
7 mm
×
7 mm
– MII—media independent interface to connect ethernet
controller to external PHY; includes output clock for
external PHY
• External Bus
– Mini-FlexBus—Multi-function external bus interface;
supports up to 1 MB memories, gate-array logic, simple
slave device or glueless interfaces to standard
chip-selected asynchronous memories
– Programmable options: access time per chip select, burst
and burst-inhibited transfers per chip select, transfer
direction, and address setup and hold times
• Power-Saving Modes
– Two low-power stop modes, one of which allows limited
use of some peripherals (ADC, KBI, RTC)
– Reduced-power wait mode shuts off CPU and allows
full use of all peripherals; FEC can remain active and
conduct DMA transfers to RAM and assert an interrupt
to wake up the CPU upon completion
– Low-power run and wait modes allow peripherals to run
while the voltage regulator is in standby
– Peripheral clock enable register can disable clocks to
unused modules, thereby reducing currents
– Low-power external oscillator that can be used in stop3
mode to provide accurate clock source to active
peripherals
– Low-power real-time counter for use in run, wait, and
stop modes with internal and external clock sources
– 6
μs
typical wake-up time from stop3 mode
– Pins and clocks to peripherals not available in smaller
packages are automatically disabled for reduced current
consumption; no user interaction is needed
• Clock Source Options
– Oscillator (XOSC) — Loop-control pierce oscillator;
crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 25 MHz
– Multi-Purpose Clock Generator (MCG) — Flexible
clock source module with either frequency-locked-loop
(FLL) or phase-lock loop (PLL) clock options. FLL can
be controlled by internal or external reference and
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
•
•
•
•
includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and
voltage. PLL derives a higher accuracy clock source derived by an external reference
System Protection
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus
clock
– Low-voltage detection with reset or interrupt; selectable trip points
– Illegal opcode and illegal address detection with programmable reset or exception response
– Flash block protection
Development Support
– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and
9S12x families debug modules
– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response
– 64-entry processor status and debug data trace buffer with programmable start/stop conditions
Peripherals
– ADC—Up to 12 channel, 12-bit resolution; 2.5
μs
conversion time; automatic compare function; 1.7 mV/°C temperature
sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V
– SCI—Three modules with optional 13-bit break
– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave
mode; MSB-first or LSB-first shifting
– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address;
interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing
– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or
center-aligned PWM on each channel
– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base,
time-of-day, calendar- or task-scheduling functions; free-running on-chip low-power oscillator (1 kHz) for cyclic wake-up
without external components; runs in all MCU modes
– MTIM—Two 8-bit resolution modulo timers with 8-bit prescaler
Input/Output
– Up to 70 general-purpose input/output (GPIO) pins, all with pin mux controls to select alternate functions
– 16 keyboard interrupt (KBI) pins with selectable polarity
– Hysteresis and configurable pull-up device or input filtering on all input pins; configurable slew rate and drive strength on
all output pins
– 16 Rapid GPIO pins connected to the CPU’s high-speed local bus with set, clear, and toggle functionality (PTD and PTF)
MCF51CN128 ColdFire Microcontroller Data Sheet, Rev. 4
2
Freescale Semiconductor
Table of Contents
1
2
3
MCF51CN128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .12
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .20
3.9 Multipurpose Clock Generator (MCG) Specifications . .21
3.10 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .23
3.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . . .24
3.11.1 Receive Signal Timing Specifications . . . . . . . .24
3.11.2 Transmit Signal Timing Specifications . . . . . . . .25
3.11.3 Asynchronous Input Signal Timing Specifications25
3.11.4 MII Serial Management Timing Specifications .26
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.12.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .28
3.12.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.12.4 ADC Characteristics . . . . . . . . . . . . . . . . . . . . .32
3.12.5 Flash Specifications. . . . . . . . . . . . . . . . . . . . . .35
3.13 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .36
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . .36
6.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
6.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6.3 48-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 13..Receive Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14..Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15..MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . 25
Table 16..MII Serial Management Channel Signal Timing . . . . . 26
Table 17..Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 18..TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 19..SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 20..12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 32
Table 21..12-bit ADC Characteristics (V
REFH
= V
DDAD
, V
REFL
=
V
SSAD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22..Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23..Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24..Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 25..Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Figures
Figure 1..MCF51CN128 Series Block Diagram . . . . . . . . . . . . . . 5
Figure 2..Pin Assignments in 80-Pin LQFP Package. . . . . . . . . . 6
Figure 3..Pin Assignments in 64-Pin LQFP Package. . . . . . . . . . 7
Figure 4..Pin Assignments in 48-Pin QFN Package. . . . . . . . . . . 8
Figure 5..Pull-up and Pull-down Typical Resistor Values . . . . . . 16
Figure 6..Typical Low-Side Driver (Sink) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7..Typical Low-Side Driver (Sink) Characteristics — High
Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8..Typical High-Side (Source) Characteristics — Low Drive
(PTxDSn = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9..Typical High-Side (Source) Characteristics — High Drive
(PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10..Typical Run I
DD
for FBE and FEI, I
DD
vs. V
DD
(ADC off, All Other Modules Enabled) . . . . . . . . . . . . . 19
Figure 11..Typical Crystal or Resonator Circuit: High Range and Low
Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12..Typical Crystal or Resonator Circuit: Low Range/Low
Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13..Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . 23
Figure 14..Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 24
Figure 15..MII Receive Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 16..MII Transmit Signal Timing Diagram . . . . . . . . . . . . . 25
Figure 17..MII Async Inputs Timing Diagram . . . . . . . . . . . . . . . 25
Figure 18..MII Serial Management Channel TIming Diagram . . 26
Figure 19..Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 20..IRQ/KBIPx Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21..Timer External Clock. . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22..Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . 28
Figure 23..SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 30
Figure 24..SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . 30
Figure 25..SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 31
Figure 26..SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 31
Figure 27..ADC Input Impedance Equivalency Diagram . . . . . . 33
4
5
6
7
List of Tables
Table 1.. MCF51CN128 Series Device Comparison . . . . . . . . . . .4
Table 2.. Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . .8
Table 3.. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . .12
Table 4.. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .12
Table 5.. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
Table 6.. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . .14
Table 7.. ESD and Latch-Up Protection Characteristics . . . . . . .14
Table 8.. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 9.. Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
Table 10..XOSC and ICS Specifications (Temperature Range = –40
to 85
°C
Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 11..MCG Frequency Specifications (Temperature Range = –40
to 125
°C
Ambient) . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 12..Mini-FlexBus AC Timing Specifications . . . . . . . . . . . .23
MCF51CN128 ColdFire Microcontroller Advance Information Data Sheet, Rev. 4
3
Freescale Semiconductor
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