AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVEF29F016U08SJ08-XX
8MB FLASH SIMM, based on AMD Am29F016B (Uniform Sector Flash Memory)
DESCRIPTION
AVED Memory Products AVEF29F016U08SJ08-XX is a
5.0V flash memory SIMM, composed of four CMOS 16Mbit
wide uniform sector flash memories, each organized as
2MB X 8bits, mounted on a substrate along with
decoupling capacitors. The module is an 80-pin, JEDEC
standard SIMM, organized into 2 banks of 4MB. It is me-
chanically compatible to all commercial sockets for many
memory applications.
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
V
SS
V
CC
NC
OE#
WE0#
WE1#
RESET# (optional)
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
*CE3#
*CE2#
*CE1#
CE0#
V
SS
DQ29
DQ30
DQ31
WE2#
NC
NC
A20
A19
A18
A17
A16
A15
A14
A13
A12
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
WE3#
V
SS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
NC
V
CC
PD1
PD2
PD3
PD4
PD5
PD6
PD7
V
SS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Single 5V power supply
Fast Access Time: 70, 90, 120ns(max)
JEDEC Industry Std Pinout and Architecture
Compatible with JEDEC Std (E
2
PROM)
Minimum 100,000 Write/Erase Cycles
Flexible sector architectures
“32 uniform sectors of 64 Kbytes each device”
Embedded Erase algorithm facilitates full chip
erase or any combination of designated sectors
Embedded Program algorithm facilitates write
and verification control at specified addresses
Data# Polling and Toggle Bit capability for
detection of program or erase cycle completion
Suspend Erase/Resume Feature allows a Read
cycle in another sector within the same bank
during Erase Cycle
Low Active Power Dissipation
AVEF29F016U08SJ08-XX = Tin Contact Plating
PIN NAMES
A0 - A20
DQ0 - DQ31
RESET# (optional)
CE#
OE#
WE#
Vcc
Vss
NC
Address Inputs
Data In/Out
Hardware Reset Pin
Chip Enable
Output Enable
Write Enable
5V
±
10% or
±
5% for High
Performance
Device Ground
No Connection
PRESENCE DETECT PINS (Optional)
MODULE
8MB
*These
pins are not used in this module
PD1
Vss
PD2
NC
PD3
Vss
PD4
Vss
SPEED
70ns
90ns
120ns
PD5
Vss
NC
Vss
PD6
Vss
NC
NC
PD7
NC
Vss
Vss
Revision: 1.0
Revision Date: 3/2001
Document Number:125202
Page Number: 1 of 13
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVEF29F016U08SJ08-XX
8MB FLASH SIMM, based on AMD Am29F016B (Uniform Sector Flash Memory)
BLOCK DIAGRAM
Revision: 1.0
Revision Date: 3/2001
Document Number:125202
Page Number: 2 of 13
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVEF29F016U08SJ08-XX
8MB FLASH SIMM, based on AMD Am29F016B (Uniform Sector Flash Memory)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages
Ambient Temperature
with Power Applied
Voltage with Respect to Ground
Vcc (Note 1)
A9 and OE# (Note 2)
All other pins (Note 1)
Output Short Circuit Current (Note 3)
-65
°
C to +125
°
C
-55
°
C to +125
°
C
-2.0V to + 7.0V
-2.0V to + 12.5V
-2.0V to 7.0V
200mA
OPERATING RANGES
Commerical (C) Devices
Ambient Temperature (T
C
)
Industrial (I) Devices
Ambient Temperature(T
C)
Extended (E) Devices
Ambient Temperature (T
A)
Vcc Supply Voltages
Vcc for
±
5% devices
Vcc for
±
10% devices
0
°
C to + 70
°
C
-40
°
C to + 85
°
C
-55
°
C to + 125
°
C
+4.75V to + 5.25V
+4.5V to + 5.5V
Operating ranges define those limits between which the functionality of the device is guaranteed.
Notes:
1.
Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may overshoot Vss to
-2.0V for periods of up to 20ns. Maximum DC voltage on output or I/O pins is Vcc +0.5V. During voltage transitions,
outputs may overshoot to Vcc +2.0 for periods of up to 20ns.
Minimum DC input voltage on A9 and OE# pins is -0.5V. During voltage transitions, A9 and OE# pins
may overshoot Vss to -2.0V for periods of up to 20ns. Maximum DC input voltage on pin A9 and OE# is
12.5V, which may overshoot to +13.5V for periods up to 20ns.
No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than
one second.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2.
3.
Figure 1. Maximum Negative Overshoot Waveform
Figure 2. Maximum Positive Overshoot Waveform
Revision: 1.0
Revision Date: 3/2001
Document Number:125202
Page Number: 3 of 13
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVEF29F016U08SJ08-XX
8MB FLASH SIMM, based on AMD Am29F016B (Uniform Sector Flash Memory)
DC CHARACTERISTICS
(
CMOS Compatible)
Sym
I
LI
I
LIT
I
LO
I
CC1
I
CC2
I
CC3
V
IL
V
IH
V
ID
V
OL
V
OH1
V
OH2
V
LK0
Description
Input Load Current
A9 Input Load Current
Output Leakage Current
V
CC
Read Current
(Note 1)
V
CC
Write Current
(Notes 2,3)
V
CC
Standby Current
(CE# Controlled) (Notes 4)
Input Low Voltage
Input High Voltage
Voltage for Autoselect and
Sector Protect
Output Low Voltage
Output High Voltage
Low V
CC
Lock-Out Voltage
Test Conditions
V
IN
= V
SS
to V
CC
V
CC
= V
CC
(max)
V
CC
= V
CC
(max)
A9 = 12.5V
V
OUT
= V
SS
to V
CC
V
CC
= V
CC
(max)
CE# =V
IL
, OE# =V
IH
CE# = V
IL
, OE# = V
IH
V
CC
= V
CC (max),
CE# = VCC
±
0.5V,
Min
Typ
Max
±
4.0
50
±
4.0
Unit
µA
µA
µA
mA
mA
µA
V
V
V
V
V
100
120
4
-0.5
0.7 x V
CC
11.5
160
160
20
0.8
V
CC
+0.3
12.5
0.45
VCC = 5.0V
I
OL
=12.0mA,
V
CC
= V
CC
(min)
I
OH
=-2.5mA,V
CC
=V
CC
(min)
I
OH
=-100µA,V
CC
=V
CC
(min)
0.85 V
CC
V
CC
- 0.4
3.2
4.2
V
Notes:
1. The I
CC
current listed is typically less than 1mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Erase or Embedded Program algorithm is in progress.
3. Not 100% tested.
4. Icc3 and Icc4 = 20uA at extended temperature(>+85
°
C).
Revision: 1.0
Revision Date: 3/2001
Document Number:125202
Page Number: 4 of 13
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AVEF29F016U08SJ08-XX
8MB FLASH SIMM, based on AMD Am29F016B (Uniform Sector Flash Memory)
AC CHARACTERISTICS
Read-Only Operations
JEDEC
t
AVAV
t
AVQV
t
ELQV
t
GLQV
Std.
t
RC
t
ACC
t
CE
t
OE
t
OEH
Description
Read Cycle Time (Note1)
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
Output Enable Hold Time
(Note1)
Read
Toggle and Data # Polling
(CE#, OE# = V
IL)
(OE# = V
IL)
Min
Max
Max
Max
Min
Min
Max
Max
Min
-75
70
70
70
40
0
10
20
20
0
- 90
90
70
90
90
0
10
70
20
20
0
-120
120
120
120
50
0
10
30
30
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
70
40
70
t
EHQZ
t
GHQZ
t
AXQX
tDF
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
Output Hold Time From Addresses CE# or
OE#, Whichever Occurs First
t
DF
tOH
Note:
1. Not 100% tested.
Figure 3. Read Operations Timings
Revision: 1.0
Revision Date: 3/2001
Document Number:125202
Page Number: 5 of 13
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