ASM1232LP, ASM1232LPS
5 V
mP
Power Supply
Monitor and Reset Circuit
Description
The ASM1232LP/LPS is a fully integrated microprocessor
Supervisor. It can halt and restart a “hung−up” microprocessor, restart
a microprocessor after a power failure. It has a watchdog timer and
external reset override.
A precision temperature−compensated reference and comparator
circuits monitor the 5 V, V
CC
input voltage status. During power−up or
when the V
CC
power supply falls outside selectable tolerance limits,
both RESET and RESET become active. When V
CC
rises above the
threshold voltage, the reset signals remain active for an additional
250 ms minimum, allowing the power supply and system
microprocessor to stabilize. The trip point tolerance signal, TOL,
selects the trip level tolerance to be either 5% or 10%.
Each device has both a push−pull, active HIGH reset output and an
open drain active LOW reset output. A debounced manual reset input,
PBRST, activates the reset outputs for a minimum period of 250 ms.
There is a watchdog timer to stop and restart a microprocessor that is
“hung−up”. The watchdog timeouts periods are selectable: 150 ms,
610 ms and 1200 ms. If the ST input is not strobed LOW before the
time−out period expires, a reset is generated.
Devices are available in 8−pin DIP, 16−pin SO and compact 8−pin
MicroSO packages.
Features
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PDIP−8
P SUFFIX
CASE 646AA
MICRO−8
U SUFFIX
CASE 846AA
SOIC−8
S SUFFIX
CASE 751BD
SOIC−16
S SUFFIX
CASE 751BG
PIN CONFIGURATIONS
1
PBRST
ASM1232LP
ASM1232LPS−2
ASM1232LPU
TD
TOL
GND
V
CC
ST
RESET
RESET
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TD
NC
TOL
NC
GND
ASM1232LPS
5 V Supply Monitor
Selectable Watchdog Period
Debounce Manual Push−button Reset Input
Precision Temperature−compensated Voltage Reference and
Comparator
Power−up, Power−down and Brown Out Detection
250 ms Minimum Reset Time
Active LOW Open Drain Reset Output and Active HIGH Push−pull
Output
Selectable Trip Point Tolerance: 5% or 10%
Low−cost Surface Mount Packages: 8−pin/16−pin SO, 8−pin DIP and
8−pin Micro SO Packages
Wide Operating Temperature
−40°C
to +85°C (N Suffixed Devices)
NC
PBRST
NC
DIP/SO/MicroSO
(Top View)
1
NC
V
CC
NC
ST
NC
RESET
NC
RESET
Applications
Microprocessor Systems
Computers
Controllers
Portable Equipment
Intelligent Instruments
Automotive Systems
SO
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2011
August, 2011
−
Rev. 3
1
Publication Order Number:
ASM1232LP/D
ASM1232LP, ASM1232LPS
Figure 1. Typical Operating Circuit
Figure 2. Block Diagram
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ASM1232LP, ASM1232LPS
Table 1. PIN DESCRIPTION
Pin #
8−Pin Package
1
2
3
4
5
Pin #
16−Pin Package
2
4
6
8
9
Pin
Name
PBRST
T
D
T
OL
GND
RESET
Function
Debounced manual pushbutton RESET input.
Watchdog time delay selection. (t
TD
= 150 ms for T
D
= GND, t
TD
= 610 ms
for T
D
= Open, and t
TD
= 1200 ms for T
D
= V
CC
).
Selects 5% (T
OL
connected to GND) or 10% (T
OL
connected to V
CC
) trip
point tolerance.
Ground.
Active HIGH reset output. RESET is active:
1. If V
CC
falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by T
D
expires.
4. During power−up.
Active LOW reset output. (See RESET).
Strobe input.
5 V power.
No internal connection.
6
7
8
11
13
15
1,3,5,7,10,12,14,16
RESET
ST
V
CC
NC
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on V
CC
(Note 1)
Voltage on ST, TD (Note 1)
Voltage on PBRST, RESET, RESET (Note 1)
Operating Temperature Range (N suffixed devices)
Operating Temperature Range (others)
Soldering Temperature (for 10 sec)
Storage Temperature
ESD rating
HBM
MM
−55
Min
−0.5
−0.5
−0.5
−40
0
Max
7
V
CC
+ 0.5
V
CC
+ 0.5
+85
70
+260
+125
2
200
Unit
V
V
V
°C
°C
°C
°C
KV
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Voltages are measured with respect to ground
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ASM1232LP, ASM1232LPS
Table 3. DC ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, 4.5 V
≤
V
CC
≤
5.5 V and over the operating
temperature range of 0°C to 70°C (−40°C to +85°C. for N devices). All Voltages are referenced to ground.)
Parameter
Supply Voltage
ST and PBRST Input High Level
ST and PBRST Input Low Level
V
CC
Trip Point (T
OL
= GND)
V
CC
Trip Point (T
OL
= V
CC
)
Watchdog Timeout Period
Watchdog Timeout Period
Watchdog Timeout Period
Output Voltage
Output Current
Output Current
Input Leakage
RESET Low Level
Internal Pull−up Resistor
Operating Current (CMOS)
Input Capacitance
Output Capacitance
PBRST Manual Reset
Minimum Low Time
Reset Active Time
ST Pulse Width
V
CC
Fail Detect to RESET or RESET
V
CC
Slew Rate
PBRST Stable LOW to RESET and
RESET Active
V
CC
Detect to RESET or RESET inactive
V
CC
Slew Rate
I
CC1
C
IN
C
OUT
t
PB
t
RST
t
ST
t
RPD
t
F
t
PDLY
t
RPU
t
R
t
RISE
= 5
ms
4.25 V to 4.75 V
250
0
610
4.75 V to 4.25 V
300
20
1000
(Note 5)
PBRST = V
IL
20
250
20
5
8
610
1000
ms
ns
ms
ms
ms
ms
ns
Symbol
V
CC
V
IH
V
IL
V
CCTP
V
CCTP
t
TD
t
TD
t
TD
V
OH
I
OH
I
OL
I
IL
V
OL
T
D
= GND
T
D
= V
CC
T
D
Floating
I =
−500
mA
(Note 4)
Output = 2.4 V
(Note 3)
Output = 0.4 V
(Note 2)
(Note 4)
(Note 2)
40
30
5
10
Conditions
Min
4.5
2
−0.3
4.50
4.25
62.5
500
250
V
CC
−
0.5
−8
10
−1.0
1.0
0.4
4.62
4.37
150
1200
610
V
CC
−
0.1
−10
Typ
Max
5.5
V
CC
+ 0.3
0.8
4.74
4.49
250
2000
1000
Unit
V
V
V
V
V
ms
ms
ms
V
mA
mA
mA
V
kW
mA
pF
pF
ms
2. PBRST is internally pulled HIGH to V
CC
through a nominal 40 kW resistor.
3. RESET is an open drain output.
4. RESET remains within 0.5 V of V
CC
on power−down until V
CC
falls below 2 V. RESET remains within 0.5 V of ground on power−down until
V
CC
falls below 2.0 V.
5. Must not exceed the minimum watchdog time−out period (t
TD
). The watchdog circuit cannot be disabled. To avoid a reset, ST must be strobed.
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ASM1232LP, ASM1232LPS
Detailed Description
Trip Point Tolerance Selection
The ASM1232LP/LPS monitors the microprocessor or
micro controller power supply and generates reset signal,
both active HIGH and Active LOW, that halt processor
operation whenever the power supply voltage levels are
outside a predetermined tolerance.
RESET and RESET outputs
RESET is an active HIGH signal developed by a CMOS
push−pull output stage and is the logical opposite to RESET.
RESET is an active LOW signal. It is developed with an
open drain driver. A pull up resistor of typical value 10 kW
to 50 kW is required to connect with the output.
The TOL input is used to determine the level V
CC
can vary
below 5 V without asserting a reset. With TOL connected to
V
CC
, RESET and RESET become active whenever V
CC
falls below 4.5 V. RESET and RESET become active when
the V
CC
falls below 4.75 V if TOL is connected to ground.
After V
CC
has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250 ms. On power−down, once V
CC
falls below the
reset threshold RESET stays LOW and is guaranteed to be
0.4 V or less until V
CC
drops below 1.2 V. The active HIGH
reset signal is valid down to a V
CC
level of 1.2 V also.
TRIP Point Voltage (V)
Tolerance Select
TOL = V
CC
TOL = GND
Tolerance
10%
5%
Min
4.25
4.5
Nom
4.37
4.62
Max
4.49
4.74
Figure 3. Timing Diagram: Power Up
Figure 4. Timing Diagram: Power Down
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