19-4148; Rev 2; 8/10
KIT
ATION
EVALU
BLE
AVAILA
2.5/5.0/8.0Gbps PCIe Passive Switches
General Description
The MAX4889B/MAX4889C high-speed passive switch-
es route PCI Express
®
(PCIe) data between two possi-
ble destinations in desktop or notebook PCs. The
MAX4889B/MAX4889C are quad double-pole/double-
throw (4 x DPDT) switches ideal for switching four half
lanes of PCIe data between two destinations. The
MAX4889B/MAX4889C feature a single digital control
input (SEL) to switch signal paths.
The MAX4889C is intended for use in systems (e.g.,
SAS) where both the input and output are capacitively
coupled, and provides a 10µA (typ) source current and
a 60kΩ (typ) internal biasing resistor to GND at the
_OUT_ terminals.
The MAX4889B/MAX4889C are fully specified to oper-
ate from a single +3.3V (typ) power supply. Both
devices are available in an industry-standard 3.5mm x
9.0mm, 42-pin TQFN package. These devices operate
over the -40°C to +85°C extended temperature range.
♦
Single +3.3V Power-Supply Voltage
♦
Support PCIe Gen I, Gen II, and Gen III Data Rates
♦
Supports SAS I, SAS II, and SAS 6.0Gbps
(MAX4889C)
♦
Superior Return Loss
Better than -10dB (typ) at 5.0GHz
♦
Small 3.5mm x 9.0mm, 42-Pin TQFN Package
♦
Industry-Standard Pinouts
Features
MAX4889B/MAX4889C
Applications
Desktop PCs
Notebook PCs
Servers
Video Graphics Cards—SLI
®
(Scaled Link Interface) and CrossFire™
PCI Express is a registered service mark of PCI-SIG Corporation.
SLI is a registered trademark of NVIDIA Corporation.
CrossFire is a trademark of ATI Technologies, Inc.
PART
MAX4889BETO+
MAX4889CETO+
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
42 TQFN-EP*
42 TQFN-EP*
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Typical Operating Circuit appears at end of data sheet.
Pin Configuration
TOP VIEW
COUTA+
DOUTA+
AOUTA+
BOUTA+
COUTA-
DOUTA-
DOUTB+
AOUTA-
BOUTA-
GND
GND
GND
GND
GND
21 V
CC
20 GND
19 V
CC
18 GND
DOUTB-
V
CC
V
CC
38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
V
CC
39
GND 40
V
CC
41
GND 42
1
AIN+
*EP
+
2
AIN-
3
AOUTB+
4
AOUTB-
5
BIN+
6
BIN-
7
BOUTB+
8
BOUTB-
9
V
CC
CIN-
CIN+
COUTB+
COUTB-
DIN+
DIN-
MAX4889B
MAX4889C
10 11 12 13 14 15 16 17
TQFN
*CONNECT EXPOSED PAD TO GROUND.
________________________________________________________________
Maxim Integrated Products
V
CC
SEL
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2.5/5.0/8.0Gbps PCIe Passive Switches
MAX4889B/MAX4889C
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
V
CC
...........................................................................-0.3V to +4V
SEL, _IN_, _OUTA_, _OUTB_ (Note 1) .......-0.3V to (V
CC
+ 0.3V)
Continuous Current (AIN_ to AOUTA_/AOUTB_, BIN_ to
BOUTA_/BOUTB_, CIN_ to COUTA_/COUTB_, DIN_ to
DOUTA_/DOUTB_) .........................................................±70mA
Peak Current (AIN_ to AOUTA_/AOUTB_, BIN_ to
BOUTA_/BOUTB_, CIN_ to COUTA_/COUTB_, DIN_ to
DOUTA_/DOUTB_)
(pulsed at 1ms, 10% duty cycle)..............................±70mA
Continuous Current (SEL).................................................±10mA
Peak Current (SEL)
(pulsed at 1ms, 10% duty cycle)..................................±10mA
Continuous Power Dissipation (T
A
= +70°C) for multilayer board:
42-Pin TQFN (derate 35.7mW/°C above +70°C) .......2857mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Package Junction-to-Ambient Thermal Resistance
(θ
JA
) (Note 2) ............................................................28.0°C/W
Package Junction-to-Case Thermal Resistance
(θ
JC
) (Note 2) ..............................................................2.0°C/W
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1:
Signals on SEL, _IN_, _OUTA_, _OUTB_ exceeding V
CC
or GND are clamped by internal diodes. Limit forward-diode current
to maximum current rating.
Note 2:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.3V ±10%, T
A
= T
MIN
to T
MAX,
unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise
noted.) (Note 3)
PARAMETER
DC PERFORMANCE
Analog Signal Range
_IN_,
_OUTA_,
_OUTB_
R
ON
R
ON
R
ON
R
FLAT (ON)
V
CC
= +3.0V, I
_IN_
= 15mA, V
_OUTA_
,
V
_OUTB_
= 0V, 1.2V
V
CC
= +3.0V, I
_IN_
= 15mA, V
_OUTA_
,
V
_OUTB_
= 0V (Notes 4, 5)
V
CC
= +3.0V, I
_IN_
= 15mA, V
_OUTA_
,
V
_OUTB_
= 0V (Notes 4, 5)
V
CC
= +3.0V, I
_IN_
= 15mA, V
_OUTA_
,
V
_OUTB_
= 0V, 1.2V (Notes 5, 6)
-1
-0.3
V
CC
-
1.8
6.4
0.1
0.2
0.3
+1
μA
8.4
0.5
V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
On-Resistance
On-Resistance Match Between
Pairs of Same Channel
On-Resistance Match Between
Channels
On-Resistance Flatness
_OUTA_ or _OUTB_ Off-Leakage
Current
_IN_ On-Leakage Current
I
_OUTA_ (OFF)
, V
CC
= +3.6V, V
_IN_
= 0V, 1.2V, V
_OUTA_
I
_OUTB_ (OFF)
or V
_OUTB_
= 1.2V, 0V (MAX4889B)
I
_IN_ (ON)
V
CC
= +3.6V, V
_IN_
= 0V, 1.2V, V
_OUTA_
or V
_OUTB_
= V
_IN_
or unconnected
(MAX4889B)
All other ports are unconnected
(MAX4889C)
All other ports are unconnected
(MAX4889C)
-1
+1
μA
Output Short-Circuit Current
Output Open-Circuit Voltage
5
0.2
0.6
15
0.9
μA
V
2
_______________________________________________________________________________________
2.5/5.0/8.0Gbps PCIe Passive Switches
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.3V ±10%, T
A
= T
MIN
to T
MAX,
unless otherwise noted. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise
noted.) (Note 3)
PARAMETER
AC PERFORMANCE
SEL-to-Switch Turn-On Time
SEL-to-Switch Turn-Off Time
Propagation Delay
Output Skew Between Pairs
Output Skew Between Same Pair
Differential Return Loss (Note 5)
Differential Insertion Loss (Note 5)
Differential Crosstalk (Note 5)
t
ON_SEL
t
OFF_SEL
t
PD
t
SKEW1
t
SKEW2
S
DD11
S
DD21
S
DDCTK
Z
S
= Z
L
= 50
Z
S
= Z
L
= 50 , Figure 1
Z
S
= Z
L
= 50 , Figure 2
Z
S
= Z
L
= 50 , Figure 2
Z
S
= Z
L
= 50 , Figure 2
0Hz < f
2.8GHz
5.0GHz
-14
-8
-3
dB
-40
-30
-25
-15
-12
-12
1.4
0.6
130
3.0
V
SEL
= 0V or V
CC
3.6
1
V
V
mV
V
mA
dB
5.0GHz
dB
5.0GHz
dB
2.8GHz < f
f > 5.0GHz
See Table 1
0Hz < f
2.5GHz
2.5GHz < f
f > 5.0GHz
0Hz < f
Differential Off-Isolation (Note 5)
CONTROL INPUT (SEL)
Input Logic High
Input Logic Low
Input Logic Hysteresis
POWER SUPPLY
Power-Supply Range
V
CC
Supply Current
V
CC
I
CC
V
IH
V
IL
V
HYST
S
DD21_OFF
2.5GHz
2.5GHz < f
f > 5.0GHz
80
15
50
50
10
ns
ns
ps
ps
ps
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX4889B/MAX4889C
Note 3:
All units are 100% production tested at T
A
= +85°C. Limits over the operating temperature range are guaranteed by design
and characterization and are not production tested.
Note 4:
ΔR
ON
= R
ON (MAX)
- R
ON (MIN)
.
Note 5:
Guaranteed by design, not production tested.
Note 6:
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal range.
Table 1. Insertion Loss Mask
FREQUENCY RANGE
(GHz)
0–2.5
2.5–5
5 or greater
MAXIMUM INSERTION
LOSS (dB)
14
25
6
5
8
5
f
GHz
+ 0.6
f
GHz
- 1.0
f
GHz
- 3.0
_______________________________________________________________________________________
3
2.5/5.0/8.0Gbps PCIe Passive Switches
MAX4889B/MAX4889C
Test Circuits/Timing Diagrams
SOURCE
LOAD
MAX4889B/
MAX4889C
Z
S
V
OUT
Z
L
SEL
Σ
SEL
50%
50%
90%
V
OUT
10%
t
ON_SEL
t
OFF_SEL
THE FREQUENCY OF THE SIGNAL SHOULD BE ABOVE THE HIGHPASS FILTER CORNER OF THE COUPLING CAPACITORS.
Figure 1. Switching Time
4
_______________________________________________________________________________________
2.5/5.0/8.0Gbps PCIe Passive Switches
Test Circuits/Timing Diagrams (continued)
SOURCE
LOAD
MAX4889B/MAX4889C
MAX4889B/
MAX4889C
Z
S
V
S+
V
OUTp
Z
L
V
OUTn
Z
L
Σ
V
S-
Z
S
Σ
SEL
Z
S
V
SC+
CALIBRATION
V
CALp
Z
L
Σ
V
SC-
Z
S
TRACES
V
CALn
Z
L
Σ
V
CALp
- V
CALn
50%
50%
V
OUTp
- V
OUTn
50%
50%
t
PDr
t
PDf
t
PD
= max (t
PDr
, t
PDf
)
V
OUTp
VCM
VCM
V
OUTn
VCM
VCM
t
SKEW
= max (t
SK1
, t
SK2
)
t
SK1
t
SK2
THE FREQUENCY OF THE SIGNALS SHOULD BE APPROXIMATELY 1/20 OF THE LOWEST DATA RATE.
Figure 2. Propagation Delay and Output Skew
_______________________________________________________________________________________
5
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