FemtoClock
®
Crystal-to-LVDS Frequency
Synthesizer
844003I-04
Datasheet
General Description
The 844003I-04 is a 3 differential output LVDS Synthesizer designed
to generate Ethernet reference clock frequencies. Using a
19.44MHz, 20MHz or 25MHz, 18pF parallel resonant crystal, the
following frequencies can be generated based on the settings of four
frequency select pins (DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz,
622.08MHz, 312.5MHz, 250MHz, 156.25MHz, 125MHz and
100MHz. The 844003I-04 has two output banks, Bank A with one
differential LVDS output pair and Bank B with two differential LVDS
output pairs.
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above. The
844003I-04 uses IDT’s 3
RD
generation low phase noise VCO
technology and can achieve 1ps or lower typical rms phase jitter,
easily meeting Ethernet jitter requirements. The 844003I-04 is
packaged in a 32-pin VFQFN package.
Features
•
•
•
•
•
•
•
•
•
Three LVDS outputs on two banks, Bank A with one LVDS pair
and Bank B with 2 LVDS output pairs
Using a 19.44MHz, 20MHz, or 25MHz crystal, the two output
banks can be independently set for 625MHz, 622.08MHz,
312.5MHz, 250MHz, 156.25MHz, 125MHz or 100MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz to 680MHz
RMS phase jitter at 125MHz (1.875MHz – 20MHz):
0.50ps (typical)
Full 3.3V output supply mode
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement part use 8T49N241
Pin Assignment
REF_CLK
V
DD
nc
V
DDO_A
V
DDA
V
DD
nc
nc
32 31 30 29 28 27 26 25
GND
XTAL_IN
XTAL_OUT
XTAL_SEL
VCO_SEL
MR
GND
1
2
3
4
5
6
7
8
9
DIV_SELA1
24
QA0
nQA0
GND
QB0
nQB0
QB1
nQB1
V
DDO_B
844003I-04
32 Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
23
22
21
20
19
18
17
Block Diagram
OEA
DIV_SELA[1:0]
VCO_SEL
Pullup
Pulldown:Pullup
Pullup
nc
10 11 12 13 14 15 16
FB_DIV
DIV_SELA0
DIV_SELB1
DIV_SELB0
GND
OEB
OEA
QA0
Pulldown
REF_CLK
0
0
XTAL_IN
00
01
10
11
÷2
÷4
(default)
÷5
÷8
nQA0
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
490-680MHz
1
QB0
FB_DIV
0 = ÷25 (default)
1 = ÷32
00
01
10
11
÷1
÷2
(default)
÷3
÷4
nQB0
QB1
nQB1
FB_DIV
DIV_SELB[1:0]
MR
OEB
Pulldown
Pulldown:Pullup
Pulldown
Pullup
©2016 Integrated Device Technology, Inc.
1
Revision C, November 10, 2016
844003I-04 Datasheet
Table 1. Pin Descriptions
Number
1, 7, 13, 22
2,
3
Name
GND
XTAL_IN
XTAL_OUT
Power
Input
Type
Description
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a
single-ended reference clock.
Pullup
Crystal select pin. Selects between the single-ended REF_CLK or crystal interface.
Has an internal pullup resistor so the crystal interface is selected by default.
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset,
(except for ÷1 state, when the device is configured as a buffer), causing the true
outputs QXx to go low and the inverted outputs nQXx to go high. When logic LOW,
the internal dividers and the outputs are enabled. MR has an internal pulldown
resistor so the power-up default state of outputs and dividers are enabled.
LVCMOS/LVTTL interface levels.
No connect.
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Division select pin for Bank A. Default = LOW. LVCMOS/LVTTL interface levels.
Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels.
Division select pin for Bank B. Default = LOW. LVCMOS/LVTTL interface levels.
Division select pin for Bank B. Default = HIGH. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32. LVCMOS/LVTTL interface levels.
Output enable Bank B. Active High output enable. When logic HIGH, the output
pair on Bank B is enabled. When logic LOW, the output pair is in a high-
impedance state. Has an internal pullup resistor so the default power-up state of
the outputs is enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair on Bank A is enabled. When logic LOW, the output pair is in a high-
impedance state. Has an internal pullup resistor so the default power-up state of
the outputs is enabled. LVCMOS/LVTTL interface levels.
Output power supply pin for Bank B outputs.
Differential Bank B output pair. LVDS interface levels.
Differential Bank B output pair. LVDS interface levels.
Differential Bank A output pair. LVDS interface levels.
Output supply pin for Bank A outputs.
Core supply pins.
Analog supply pin.
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to low
state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL
interface levels.
4
XTAL_SEL
Input
5
VCO_SEL
Input
Pullup
6
MR
Input
Pulldown
8, 26, 29, 30
9
10
11
12
14
nc
DIV_SELA1
DIV_SELA0
DIV_SELB1
DIV_SELB0
FB_DIV
Unused
Input
Input
Input
Input
Input
15
OEB
Input
Pullup
16
OEA
Input
Pullup
17
18, 19
20, 21
23, 24
25
27, 31
28
32
V
DDO_B
nQB1, QB1
nQB0, QB0
nQA0, QA0
V
DDO_A
V
DD
V
DDA
REF_CLK
Power
Output
Output
Output
Power
Power
Power
Input
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
©2016 Integrated Device Technology, Inc.
2
Revision C, November 10, 2016
844003I-04 Datasheet
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. Output Bank A Configuration
Select Function Table
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Outputs
QA0, nQA0
÷2
÷4 (default)
÷5
÷8
DIV_SELB1
0
0
1
1
Table 3B. Output Bank B Configuration
Select Function Table
Inputs
DIV_SELB0
0
1
0
1
Outputs
QB[0:1], nQB[0:1]
÷1
÷2 (default)
÷3
÷4
Table 3C. OEA Select Function Table
Input
OEA
0
1
Outputs
QA0, nQA0
High-Impedance
Active (default)
Table 3D. OEB Select Function Table
Input
OEB
0
1
Outputs
QB[0:1], nQB[0:1]
High-Impedance
Active (default)
Table 3E. Feedback Divider Configuration
Select Function Table
Input
FB_DIV
0
1
Feedback Divide
÷25 (default)
÷32
©2016 Integrated Device Technology, Inc.
3
Revision C, November 10, 2016
844003I-04 Datasheet
Table 3F. Bank A Frequency Table
Inputs
Crystal Frequency
(MHz)
25
20
25
24
20
25
25
24
20
19.44
15.625
19.44
18.75
15.625
15.625
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DIV_SELA1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
DIV_SELA0
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
Bank A
Output Divider
2
2
4
4
4
5
8
8
8
2
2
4
4
4
5
8
8
8
M/N
Multiplication
Factor
12.5
12.5
6.25
6.25
6.25
5
3.125
3.125
3.125
16
16
8
8
8
6.4
4
4
4
QA0, nQA0
Output Frequency
(MHz)
312.5
250
156.25
150
125
125
78.125
75
62.5
311.04
250
155.52
150
125
100
77.76
75
62.5
©2016 Integrated Device Technology, Inc.
4
Revision C, November 10, 2016
844003I-04 Datasheet
Table 3G. Bank B Frequency Table
Inputs
Crystal Frequency
(MHz)
25
25
20
22.5
25
24
20
19.44
19.44
15.625
18.75
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
1
1
1
1
1
1
1
DIV_SELB1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
DIV_SELB0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
32
32
32
32
32
32
32
Bank B
Output Divider
1
2
2
3
4
4
4
1
2
2
3
4
4
4
M/N
Multiplication
Factor
25
12.5
12.5
8.333
6.25
6.25
6.25
32
16
16
10.667
8
8
8
QBx/ nQBx
Output Frequency
(MHz)
625
312.5
250
187.5
156.25
150
125
622.08
311.04
250
200
155.52
150
125
©2016 Integrated Device Technology, Inc.
5
Revision C, November 10, 2016
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