Si53159
PCI-E
XPRESS
G
EN
1, G
EN
2, & G
EN
3 N
INE
O
UTPUT
F
ANOUT
B
UFFER
Features
PCI-Express Gen 1, Gen 2, and
Gen 3 compliant
Supports Serial-ATA (SATA) at
100 MHz
Low power push-pull differential
output buffers
No termination resistors required
Output enable pins for all
buffered clocks
Up to nine buffered clocks
100 to 210 MHz clock input range
I
2
C support with readback
capabilities
Supports spread spectrum input
Extended temperature:
–40 to 85
o
C
3.3 V power supply
48-pin QFN package
Ordering Information:
See page 18.
Applications
Network attached storage
Multi-function printers
Wireless access point
Servers
NC
Pin Assignments
VSS_DIFF
VSS_CORE
CKPWRGD/PDB
1
VDD_CORE
SDATA
38
DIFFIN
DIFFIN
NC
NC
48
47
46
45
44
43
NC
42
41
40
39
37
36
35
34
33
32
31
DIFF8
DIFF8
VDD_DIFF
DIFF7
DIFF7
DIFF6
DIFF6
VSS_DIFF
DIFF5
DIFF5
DIFF4
The Si53159 is a high-performance, low additive, PCIe clock buffer that
can fan out nine PCIe clocks. The clock outputs are compliant to PCIe
Gen 1, Gen 2, and Gen 3 specifications. The device has six hardware
output enable control pins for enabling and disabling differential outputs.
The small footprint and low power consumption makes the Si53159 the
ideal clock solution for consumer and embedded applications.
VDD_DIFF
VDD_DIFF
OE_DIFF0
1
OE_DIFF1
1
VDD_DIFF
VSS_DIFF
VSS_DIFF
OE_DIFF2
1
OE_DIFF3
1
OE_DIFF[4:5]
1
OE_DIFF[6:8]
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
49
GND
SCLK
30
29
28
27
26
25 DIFF4
Description
Functional Block Diagram
VDD_DIFF
VSS_DIFF
VDD_DIFF
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
DIFF0
DIFF1
DIFF2
DIFFIN
DIFF3
DIFFIN
DIFF4
DIFF5
SCLK
SDATA
OE [8:0]
Control & Memory
Control
RAM
Patents pending
DIFF6
DIFF7
DIFF8
Rev. 1.0 5/12
Copyright © 2012 by Silicon Laboratories
VDD_DIFF
VSS_DIFF
DIFF0
DIFF0
DIFF1
DIFF1
DIFF2
DIFF2
DIFF3
DIFF3
Si53159
Si53159
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. CKPWRGD/PDB (Power Down) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. PDB (Power Down) Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3. PDB Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.4. OE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.5. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.6. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4.1. I
2
C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5. Pin Descriptions: 48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev. 1.0
3
Si53159
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
3.3 V Operating Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Leakage Current
Input Low Leakage Current
High-impedance Output
Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Power Down Current
Dynamic Supply Current in
Fanout Mode
Symbol
VDD core
V
IH
V
IL
V
IHI2C
V
ILI2C
I
IH
I
IL
I
OZ
C
IN
C
OUT
L
IN
I
DD
_
PD
I
DD_3.3V
All outputs enabled,
5” traces; 2 pF load,
frequency at 100 MHz
Test Condition
3.3 ± 5%
Control input pins
Control input pins
SDATA, SCLK
SDATA, SCLK
Except internal pull-down
resistors, 0 < V
IN
< V
DD
Except internal pull-up
resistors, 0 < V
IN
< V
DD
Min
3.135
2.0
V
SS
– 0.3
2.2
—
—
–5
–10
1.5
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3.465
V
DD
+ 0.3
0.8
—
1.0
5
—
10
5
6
7
1
60
Unit
V
V
V
V
V
A
A
A
pF
pF
nH
mA
mA
4
Rev. 1.0
Si53159
Table 2. AC Electrical Specifications
Parameter
DIFFIN at 0.7 V
DIFFIN and DIFFIN
Rising/Falling Slew Rate
Differential Input High Voltage
Differential Input Low Voltage
Crossing Point Voltage at 0.7 V
Swing
Vcross Variation Over All edges
Differential Ringback Voltage
Time before Ringback Allowed
Absolute Maximum Input Voltage
Absolute Minimum Input Voltage
DIFFIN and DIFFIN Duty Cycle
Rise/Fall Matching
DIFF at 0.7 V
Duty Cycle
Clock Skew
PCIe Gen1 Pk-Pk Jitter
PCIe Gen 2 Phase Jitter
PCIe Gen 3 Phase Jitter
Additive Cycle to Cycle Jitter
Long-term Accuracy
Rising/Falling Slew rate
Crossing Point Voltage at 0.7 V
Swing
Enable/Disable and Setup
Clock Stabilization from Power-Up
Stopclock Set-up Time
T
STABLE
T
SS
—
10.0
—
—
1.8
—
ms
ns
T
DC
T
SKEW
Pk-Pk
RMS
GEN2
RMS
GEN3
T
CCJ
L
ACC
T
R
/ T
F
V
OX
Measured at 0 V differential
Measured at 0 V differential
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
In buffer mode.
Measured at 0 V differential
Measured at 0 V differential
Measured differentially from
±150 mV
45
—
0
0
0
0
—
—
2.5
300
—
—
—
—
—
—
20
—
—
—
55
50
10
0.5
0.5
0.10
50
100
8
550
%
ps
ps
ps
ps
ps
ps
ppm
V/ns
mV
T
R
/ T
F
Single ended measurement:
V
OL
= 0.175 to V
OH
= 0.525 V
(Averaged)
0.6
—
4
V/ns
Symbol
Condition
Min
Typ
Max
Unit
V
IH
V
IL
V
OX
V
OX
V
RB
T
STABLE
V
MAX
V
MIN
T
DC
T
RFM
Measured at crossing point V
OX
Determined as a fraction of
2 x (T
R
– T
F
)/(T
R
+ T
F
)
Single-ended measurement
Single-ended measurement
150
—
250
—
–100
500
—
—
—
—
—
—
—
—
–150
550
140
100
—
1.15
—
55
20
mV
mV
mV
mV
mV
ps
V
V
%
%
–0.3
45
—
—
—
—
Note:
Visit
www.pcisig.com
for complete PCIe specifications.
Rev. 1.0
5
Microchip MCU
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