Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Note 1:
Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= +3.6V, V
DVDD
= +1.7V, V
REFP
- V
REFN
= V
AVDD
; internal clock, single-cycle mode (SCYCLE = 1), T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25NC under normal conditions, unless otherwise noted.)
PARAMETER
STATIC PERFORMANCE
Noise-Free Resolution (Notes 2, 3)
Noise (Notes 2, 3)
Integral Nonlinearity
Zero Error
Zero Drift
Full-Scale Error
Full-Scale Error Drift
Power-Supply Rejection
ANALOG INPUTS/REFERENCE INPUTS
DC rejection
Common-Mode Rejection
Normal-Mode 50Hz Rejection
Normal-Mode 60Hz Rejection
Common-Mode Voltage Range
CMR
NMR
50
NMR
60
50Hz/60Hz rejection at 120sps
50Hz/60Hz rejection at 1sps to 15sps
LINEF = 1, for 1sps to 15sps (Notes 6, 7)
LINEF = 0, for 1sps to 15sps (Notes 6, 7)
AIN buffers disabled
90
90
144
100
100
V
GND
144
144
V
AVDD
dB
dB
V
123
dB
AVDD DC rejection
DVDD DC rejection
70
90
After self and system calibration,
V
REFP
- V
REFN
= 2.5V (Note 5)
-20
0.05
80
100
NFR
V
N
INL
120sps
10sps
120sps
10sps
At 10sps (Note 4)
After self and system calibration,
V
REFP
- V
REFN
= 2.5V
-15
-15
50
+20
18
18
2.1
0.55
+15
+15
Bits
FV
RMS
ppmFSR
ppmFSR
nV/NC
ppmFSR
ppmFSR/
NC
dB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
Maxim Integrated
MAX11209/MAX11211
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +3.6V, V
DVDD
= +1.7V, V
REFP
- V
REFN
= V
AVDD
; internal clock, single-cycle mode (SCYCLE = 1), T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Buffers disabled
Low input voltage
Buffers enabled
Absolute Input Voltage
Buffers disabled
High input voltage
Buffers enabled
DC Input Leakage
AIN Dynamic Input Current
REF Dynamic Input Current
AIN Input Capacitance
REF Input Capacitance
AIN Voltage Range
Input Sampling Rate
f
S
Sleep mode
Buffer disabled
Buffer enabled
Buffer disabled
Buffer enabled
Buffer disabled
Buffer disabled
Unipolar
Bipolar
LINEF = 0
LINEF = 1
Buffers disabled
REF Voltage Range
Buffers enabled
LINEF = 0
LINEF = 1
Input leakage current
V
IL
V
IH
V
HYS
60Hz line frequency
External Clock
55Hz line frequency
50Hz line frequency
LOGIC OUTPUTS (RDY/DOUT, GPIO1–GPIO4)
I
OL
= 1mA; also tested for V
DVDD
= 3.6V
Output Low Level
V
OL
Output High Level
Leakage Current
Output Capacitance
V
OH
I
OH
= 1mA; also tested for V
DVDD
= 3.6V
High-impedance state
High-impedance state
0.9 x
V
DVDD
Q500
9
0.7 x
V
DVDD
200
2.4576
2.25275
2.048
0.4
V
V
nA
pF
MHz
0
0.1
246
204.8
Q1
0.3 x
V
DVDD
0
-V
REF
246
204.8
V
AVDD
V
AVDD
- 0.1
V
MIN
TYP
V
GND
-
30mV
V
GND
+
100mV
V
AVDD
+
30mV
V
AVDD
-
100mV
Q1
Q1.4
Q20
Q2.1
Q30
5
7.5
V
REF
+V
REF
FA
FA/V
nA
FA/V
nA
pF
pF
V
kHz
MAX
UNITS
V
REF Sampling Rate
kHz
LOGIC INPUTS (SCLK, CLK, DIN, GPIO1–GPIO4)
Input Current
Input Low Voltage
Input High Voltage
Input Hysteresis
FA
V
V
mV
Maxim Integrated
3
MAX11209/MAX11211
18-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +3.6V, V
DVDD
= +1.7V, V
REFP
- V
REFN
= V
AVDD
; internal clock, single-cycle mode (SCYCLE = 1), T
A
= T
MIN
to T
MAX
,
unless otherwise noted. Typical values are at T
A
= +25NC under normal conditions, unless otherwise noted.)
PARAMETER
POWER REQUIREMENTS
Analog Supply
Digital Supply
Total Operating Current
AVDD Sleep Current
AVDD Operating Current
DVDD Sleep Current
DVDD Operating Current
SPI TIMING CHARACTERISTICS
SCLK Frequency
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Low to 1st SCLK Rise Setup
CS
High to 17th SCLK Setup
CS
High After 16th SCLK
Falling Edge Hold
CS
Pulse-Width High
DIN to SCLK Setup
DIN Hold After SCLK
RDY/DOUT
Transition Valid After
SCLK Fall
RDY/DOUT
Remains Valid After
SCLK Fall
RDY/DOUT
Valid Before SCLK Rise
CS
Rise to
RDY/DOUT
Disable
CS
Fall to
RDY/DOUT
Valid
f
SCLK
t
CP
t
CH
t
CL
t
CSS0
t
CSS1
t
CSH1
t
CSW
t
DS
t
DH
t
DOT
t
DOH
t
DOL
t
DOD
t
DOE
Output transition time, data changes on
falling edge of SCLK
Output hold time allows for negative edge
data read
t
DOL
= t
CL
- t
DOT
C
LOAD
= 20pF
Default value of
RDY
is 1 for minimum
specification; maximum specification for
valid 0 on
RDY/DOUT
Maximum time after
RDY
asserts to read
DATA register; t
CNV
is the time for one
conversion
0
3
40
25
40
60% duty cycle at 5MHz
200
80
80
40
40
3
40
40
0
40
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Buffers disabled
Buffers enabled
V
AVDD
V
DVDD
AVDD + DVDD
Buffers disabled
Buffers enabled
2.7
1.7
235
255
0.15
185
205
0.25
50
2
65
2
235
3.6
3.6
300
V
V
FA
FA
FA
FA
FA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DATA Fetch
Note
Note
Note
Note
2:
3:
4:
5:
t
DF
0
t
CNV
-
60 x t
CP
These specifications are not fully tested and are guaranteed by design and/or characterization.
V
AINP
= V
AINN
.
ppmFSR is parts per million of full scale.
Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 6:
For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7:
Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
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