DATASHEET
GLITCH-FREE CLOCK MULITPLEXER
Description
The ICS580-01 is a clock multiplexer (mux) designed to
switch between two clock sources with no glitches or short
pulses. The operation of the mux is controlled by an input
pin but the part can also be configured to switch
automatically if one of the input clocks stops. The part also
provides clock detection by reporting when an input clock
has stopped.
For a clock mux with zero delay and smooth switching, see
either the ICS581-01 or the ICS581-02.
ICS580-01
Features
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16-pin SOIC and 16-pin TSSOP packages available
Pb (lead) free package
No short pulses or glitches on output
Operates from 2 to 220 MHz
Low skew outputs
Clock detect feature
Ideal for systems with back-up or redundant clocks
Selectable timeouts for clock detection
Separate supply voltages allow power supply voltage
translation
Operates from 2.5 V to 5 V
Block Diagram
VDDI
VDDC
INB
CLK1
1
OE1
INA
0
CLK2
OE2
Transition
Detector
OE4
Transition
Detector
OE3
NO_INB
SELB
NO_INA
DIV
Timer
GND
IDT™ / ICS™
GLITCH-FREE CLOCK MULITPLEXER
1
ICS580-01
REV L 051310
ICS580-01
GLITCH-FREE CLOCK MULITPLEXER
CLOCK MULTIPLEXER
Pin Assignment
SELB
DIV
VDDI
INA
INB
GND
OE4
OE3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OE1
VDDC
CLK1
CLK2
NO_INA
NO_INB
GND
OE2
Timeout Selection
DIV
0
1
Nominal Timeout
600 ns
75 ns
16 pin (150 mil) SOIC
SELB
DIV
VDDI
INA
INB
GND
OE4
OE3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OE1
VDDC
CLK1
CLK2
NO_INA
NO_INB
GND
OE2
16-pin TSSOP
IDT™ / ICS™
GLITCH-FREE CLOCK MULITPLEXER
2
ICS580-01
REV L 051310
ICS580-01
GLITCH-FREE CLOCK MULITPLEXER
CLOCK MULTIPLEXER
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
SELB
DIV
VDDI
INA
INB
GND
OE4
OE3
OE2
GND
NO_INB
NO_INA
CLK2
CLK1
VDDC
OE1
Pin
Type
Input
Input
Power
Input
Input
Power
Input
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Mux select. Selects INB when high. Internal pull-up.
Time out select. See table above. Internal pull-up.
Supply for input clocks only. Can be higher than VDDC.
Input Clock A.
Input Clock B.
Connect to ground.
Output enable. Tri-states NO_INB when low. Internal pull-up.
Output enable. Tri-states NO_INA when low. Internal pull-up.
Output enable. Tri-states CLK2 when low. Internal pull-up.
Connect to ground.
Goes high when clock on INB stops.
Goes high when clock on INA stops.
Clock 2 output. Low skew compared to CLK1.
Clock 1 output. Low skew compared to CLK2.
Main chip supply. Output clocks amplitude will match this VDD.
Output enable. Tri-states CLK1 when low. Internal pull-up.
IDT™ / ICS™
GLITCH-FREE CLOCK MULITPLEXER
3
ICS580-01
REV L 051310
ICS580-01
GLITCH-FREE CLOCK MULITPLEXER
CLOCK MULTIPLEXER
Device Operation
The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is designed to
switch between two clocks, whether running or not. In the first example, clocks are running on both INA and INB.
When SELB changes, the output clock goes low after three cycles of the output clock (nominally). The output then
stays low for three cycles of the new input clock (nominally) and then starts with the new input clock. This is shown
in Figure 1.
Figure 1
INA
INB
SELB
CLK1, 2
In the second example, one of the inputs was selected and running but has since stopped (either high or low). This
is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has stopped. These signals
go high following a selectable time-out period after the clock has stopped. The timeout period is determined by the
DIV input in. The SELB pin is now changed to select the new input clock which is running. The output clock
immediately goes low and stays low for three cycles of the new input clock and then starts with the new input clock.
Figure 2 shows an example of this
Figure 2
INA
INB
SELB
Timeout
NO_INA
CLK1, 2
IDT™ / ICS™
GLITCH-FREE CLOCK MULITPLEXER
4
ICS580-01
REV L 051310
ICS580-01
GLITCH-FREE CLOCK MULITPLEXER
CLOCK MULTIPLEXER
Application Example
In the third example, the ICS580-01 is configured to automatically switch clocks when an input stops. The clock that
could stop is connected to INA while the backup clock (always running) is connected to INB. The output NO_INA is
connected to SELB. This means that when the clock on INA stops, NO_INA goes high selecting the clock on INB
which is muxed to the output after three cycles. When the clock on INA restarts, NO_INA immediately goes low,
selecting the clock on INA. The output then switches in the manner described in the first example.
The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB are
unused and are disabled by grounding OE2 and OE4. A 33Ω series termination resistor is used on the clock output
and two decoupling capacitors of 0.01µF are used. All other inputs are left floating and are therefore pulled high by
the on-chip pull-ups.
VDD
SELB
DIV
0.01µF
OE1
VDDC
CLK1
CLK2
NO_INA
NO_INB
GND
OE2
33Ω
0.01µF
VDDI
INA
INB
GND
OE4
OE3
Output Clock
Normal Clock
Backup Clock
Output Enable
Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the
appropriate output enable pin to ground.
External Components
The ICS580-01 requires two 0.01µF decoupling capacitors, one between VDDI and GND and one between VDDC
and GND. Series termination resistors of 33Ω can be used on CLK1 and CLK2.
IDT™ / ICS™
GLITCH-FREE CLOCK MULITPLEXER
5
ICS580-01
REV L 051310
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