operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each
other when instructed. Synchronous operation eliminates the
output counting spikes normally associated with asynchronous
counters.
The outputs of the four flip-flops are triggered on a low-to-high-
level transition of either count input (Up or Down). The direc-
tion of the counting is determined by which count input is pulsed
while the other count input is high.
The counters are fully programmable. The outputs may be preset
to either level by placing a low on the load input and entering
the desired data at the data inputs. The output will change to
agree with the data inputs independently of the count pulses.
Asynchronous loading allows the counters to be used as modulo-
N dividers by simply modifying the count length with the preset
inputs.
A clear input has been provided that forces all outputs to the low
level when a high level is applied. The clear function is inde-
pendent of the count and the load inputs.
The counter is designed for efficient cascading without the need
for external circuitry. The borrow output (BO) produces a low-
level pulse while the count is zero and the down input is low.
1
Similarly, the carry output (CO) produces a low-level pulse
while the count is maximum
PINOUTS
16-Pin DIP
Top View
B
Q
B
Q
A
DOWN
UP
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A
CLR
BO
CO
LOAD
C
D
16-Lead Flatpack
Top View
B
Q
B
Q
A
DOWN
UP
Q
C
Q
D
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
A
CLR
BO
CO
LOAD
C
D
FUNCTION TABLE
FUNCTION
Count Up
Count Down
Reset
Load Preset
Input
CLOCK
UP
↑
H
X
X
CLOCK
DOWN
H
↑
X
X
CLR
L
L
H
L
LOAD
H
H
X
L
LOGIC SYMBOL
(14)
CLR
(5)
UP
DOWN
LOAD
A
(4)
(11)
(15)
CTRDIV 16
CT=0
1CT=15
2+
G1
1-
G2
C3
3D
(1)
(2)
(4)
(8)
2CT=0
(12)
CO
(13)
BO
(3)
(2)
(1)
B
(10)
C
(9)
D
Q
A
Q
B
(6)
Q
C
(7)
Q
D
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publi-
cation 617-12.
LOGIC DIAGRAM
(13)
(12)
A
(15)
SQ
C
RQ
BO
CO
DOWN (4)
UP (5)
(3) Q
A
B (1)
SQ
C
RQ
(2) Q
B
C
(10)
SQ
C
RQ
(6) Q
C
D (9)
CLR (14)
SQ
C
RQ
(7) Q
D
LOAD (11)
2
OPERATIONAL ENVIRONMENT
1
PARAMETER
Total Dose
SEU Threshold
2
SEL Threshold
Neutron Fluence
LIMIT
1.0E6
80
120
1.0E14
UNITS
rads(Si)
MeV-cm
2
/mg
MeV-cm
2
/mg
n/cm
2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
DD
V
I/O
T
STG
T
J
T
LS
Θ
JC
I
I
P
D
PARAMETER
Supply voltage
Voltage any pin
Storage Temperature range
Maximum junction temperature
Lead temperature (soldering 5 seconds)
Thermal resistance junction to case
DC input current
Maximum power dissipation
LIMIT
-0.3 to 7.0
-.3 to V
DD
+.3
-65 to +150
+175
+300
20
±10
1
UNITS
V
V
°C
°C
°C
°C/W
mA
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
V
IN
T
C
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
LIMIT
4.5 to 5.5
0 to V
DD
-55 to + 125
UNITS
V
V
°C
3
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V
±
10%; V
SS
= 0V
6
, -55°C < T
C
< +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
V
IL
PARAMETER
Low-level input voltage
1
ACTS
ACS
High-level input voltage
1
ACTS
ACS
Input leakage current
ACTS/ACS
Low-level output voltage
3
ACTS
ACS
High-level output voltage
3
ACTS
ACS
Short-circuit output current
2 ,4
ACTS/ACS
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
ΔI
DDQ
Power dissipation
2, 8, 9
Quiescent Supply Current
Quiescent Supply Current Delta
ACTS
V
IN
= V
DD
or V
SS
I
OL
= 8.0mA
I
OL
= 100μA
I
OH
= -8.0mA
I
OH
= -100μA
V
O
= V
DD
and V
SS
V
IN
= V
DD
or V
SS
V
OL
= 0.4V
V
IN
= V
DD
or V
SS
V
OH
= V
DD
- 0.4V
C
L
= 50pF
V
DD
= 5.5V
For input under test
V
IN
= V
DD
- 2.1V
For all other inputs
V
IN
= V
DD
or V
SS
V
DD
= 5.5V
C
IN
C
OUT
Input capacitance
5
Output capacitance
5
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
15
15
pF
pF
2.1
10
1.6
mW/
MHz
μA
mA
-8
mA
.7V
DD
V
DD
- 0.25
-200
8
200
.5V
DD
.7V
DD
-1
1
CONDITION
MIN
MAX
0.8
.3V
DD
UNIT
V
V
IH
V
I
IN
V
OL
μA
0.40
0.25
V
V
OH
V
I
OS
I
OL
mA
mA
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V
IH
= V
IH
(min) + 20%, - 0%; V
IL
= V
IL
(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to V
IH
(min) and V
IL
(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density
≤
5.0E5 amps/cm
2
, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and V
SS
at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All ACTS specifications are valid for radiation dose
≤
1E6 rads(Si) and all ACS specifications are valid for radiation dose
≤
5E5 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
IC Design类：
VLSI Manager
Sr.ASIC Design Engineer
Sr. Layout Engineer
IC Video Process Engineer
Sr. Digital Design Engineer
Sr. Analog IC Design Engineer
Senior RF IC D ......
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