tm
TE
CH
T15V2M16B
SRAM
FEATURES
•
Access time : 45/55/70/100 ns
•
Low-power consumption
- Active: 5mA (I
CC1
)
- Stand-by: (CMOS input/output)
Max.. 15 uA for 55/70/100ns
Max.. 40 uA for 45ns
•
Equal access and cycle time
•
Single +2.7V to 3.6V Power Supply
•
TTL compatible , Tri-state output
•
Common I/O capability
•
Automatic power-down when deselected
•
Available in 44-PIN TSOP-II and 48-pin CSP
packages
•
Operating temperature :
-
-
-10 ~ +70
°C
-40 ~ +85
°C
128K X 16 LOW POWER
CMOS STATIC RAM
GENERAL DESCRIPTION
The T15V2M16B is a very Low Power CMOS
Static RAM organized as 131,072 words by 16
bits
.
This
device
is
fabricated by high
performance CMOS technology. It can be operated
under wide power supply voltage range from
+2.7V to +3.6V.
The T15V2M16B inputs and three-state
outputs are TTL compatible and allow for direct
interfacing with common system bus structures.
Data retention is guaranteed at a power supply
voltage as low as 2V.
BLOCK DIAGRAM
PART NUMBER EXAMPLES
PART NUMBER
T15V2M16B-55S
T15V2M16B-70C
T15V2M16B-55SI
T15V2M16B-70CI
PACKAGE
TSOP-II
CSP
TSOP-II
CSP
Temperature
-10 ~ +70
°C
-10 ~ +70
°C
-40 ~ +85
°C
-40 ~ +85
°C
Vcc
Vss
A0
.
.
.
DECODER
CORE
ARRAY
A16
CE
WE
OE
LB
UB
CONTROL
CIRCUIT
DATA I/O
I/O1
.
.
.
I/O16
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: NOV. 2002
Revision:A
tm
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
TE
CH
T15V2M16B
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TSOP-II
1
A
B
C
D
E
F
G
H
LB
2
OE
3
A0
4
A1
5
A2
6
NC
I/O9
UB
A3
A4
CE
I/O1
I/O10
I/O11
A5
A6
I/O2
I/O3
VSS
I/O12
NC
A7
I/O4
VCC
VCC
I/O13
NC
A16
I/O5
VSS
I/O15
I/O14
A14
A15
I/O6
I/O7
I/O16
NC
A12
A13
WE
I/O8
NC
A8
A9
A10
A11
NC
48-Ball CSP
TOP VIEW (Ball Down)
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A16 Address inputs
I/O1~I/O16 Data inputs/outputs
CE
WE
OE
SYMBOL DESCRIPTIONS
LB
UB
Lower byte (I/O 1~8)
Upper byte (I/O 9~16)
Power supply
Ground
No connection
P. 2
Publication Date: NOV. 2002
Revision:A
Chip enable
Write enable input
Output enable input
VCC
V
SS
NC
TM Technology Inc. reserves the right
to change products or specifications without notice.
tm
TE
CH
T15V2M16B
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on Any Pin Relative to VSS
Power Dissipation
Storage Temperature
Temperature Under Bias
SYM
V
R
P
D
T
STG
I
BIAS
MIN.
-0.2
-
-55
-10 / -40
MAX.
+4.6 V
1.0
+150
+70 / +85
UNIT
V
W
°C
°C
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
I/O 1~8
I/O 9~16
MODE
LB
OE
WE
UB
CE
H
X*
X*
X*
X*
High-Z
High-Z
Deselected
X*
X*
X*
H
H
High-Z
High-Z
Deselected
L
H
H
L
X*
High-Z
High-Z
Output Disabled
L
H
H
X*
L
High-Z
High-Z
Output Disabled
L
L
H
L
H
Data Out
High-Z
Lower Byte Read
L
L
H
H
L
High-Z
Data Out
Upper Byte Read
L
L
H
L
L
Data Out
Data Out
Word Read
L
X*
L
L
H
Data In
High-Z
Lower Byte Write
L
X*
L
H
L
High-Z
Data In
Upper Byte Write
L
X*
L
L
L
Data In
Data In
Word Write
*Note: X = Don’t Care (Must be low or high state), L = Low, H = High
Power
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: NOV. 2002
Revision:A
tm
-
TE
CH
T15V2M16B
RECOMMENDED OPERATING CONDITIONS
(Ta =
-10 ~ +70
°C
/
-40°C ~ 85°C)
PARAMETER
Supply Voltage
Input Voltage
SYM
Vcc
V
SS
MIN
2.7
0.0
0.7Vcc
-0.2
TYP
3.0
0.0
-
-
MAX
3.6
0.0
Vcc+0.3
0.6
UNIT
V
V
V
V
V
IH
V
IL
OPERATING CHARACTERISTICS
-
(Vcc = 2.7 to 3.6V,
V
SS
= 0V, Ta =
-10 ~ +70
°C
/
-40°C ~ 85°C)
SYM.
I
LI
TEST CONDITIONS
Vcc = Max,
V
IN
= V
SS
to Vcc
-45
-55
-70
-100
UNIT
PARAMETER
Input Leakage
Current
Output Leakage
Current
Min Max Min Max Min Max Min Max
-
1
-
1
-
1
-
1
uA
Operating Power
Supply Current
Average Operating
Current
Standby Power
Supply Current
(TTL Level)
Standby Power
Supply Current
(CMOS Level)
Output Low Voltage
Output High Voltage
CE
= V
IH
or
OE
= V
IH
I
LO
or
WE
= V
IL
V
IO
= V
SS
to Vcc
CE
= V
IL
,
WE
=V
IH,
OE
= V
IH
,
I
CC
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
Cycle time=1us,
100% duty, I
IO
=0mA,
I
CC1
CE
≤
0.2V,
V
IN
≥
V
CC
-0.2V
or V
IN
≤
0.2V
Cycle time=min,
100% duty, I
IO
=0mA,
I
CC2
CE
= V
IL,
V
IN
= V
IH
or V
IL
CE
=
V
IH
or
I
SB
LB
=
UB
=
V
IH
other input= V
IL
or
V
IH
CE
≥
Vcc-0.2V or
LB
=
UB
≥Vcc-0.2V,
I
SB1
V
IN
≤
0.2V or
V
IN
≥
Vcc-0.2V
V
OL
I
OL
= 2.1mA
V
OH
I
OH
= -1.0 mA
-
1
-
1
-
1
-
1
uA
-
3
-
3
-
3
-
3
mA
-
5
-
5
-
5
-
5
mA
-
45
-
40
-
35
-
25
mA
-
0.3
-
0.3
-
0.3
-
0.3
mA
-
40
-
15
-
15
-
15
uA
-
2.2
P. 4
0.4
-
- 0.4
2.2
-
- 0.4
2.2
-
- 0.4
2.2
-
V
V
TM Technology Inc. reserves the right
to change products or specifications without notice.
Publication Date: NOV. 2002
Revision:A
tm
TE
CH
T15V2M16B
CAPACITANCE
(f = 1 MHz, Ta = 25°C,)
PARAMETER
Input Capacitance
Input/ Output Capacitance
SYMBOL
CONDITION
V
IN
= 0V
V
IN
=
V
OUT
= 0V
MAX.
8
10
UNIT
pF
pF
C
IN
C
I/O
Note:
This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
CONDITIONS
0.6V to 0.7Vcc
3.0 ns
1.4V
C
L
=30pF+1TTL Load(45/55/70ns)
C
L
=100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
TTL
DQ
R
L
50 ohm
C
L
*
Z
0
= 50 ohm
Vt =1.4V
C
L
30 pF
Fig.A * Including Scope and Jig Capacitance
Fig.B Output Load Equivalent
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: NOV. 2002
Revision:A
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