Philips Semiconductors
Product data
Latch/flip-flop
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
FEATURES
74F373/74F374
•
8-bit transparent latch — 74F373
•
8-bit positive edge triggered register — 74F374
•
3-State outputs glitch free during power-up and power-down
•
Common 3-State output register
•
Independent register and 3-State buffer operation
•
SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is HIGH. The latch remains transparent to the data
input while E is HIGH, and stores the data that is present one set-up
time before the HIGH-to-LOW enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is LOW, latched or
transparent data appears at the output.
When OE is HIGH, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is LOW, the data in
the register appears at the outputs. When OE is HIGH, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
TYPICAL
PROPAGATION
DELAY
4.5 ns
TYPICAL SUPPLY
CURRENT
(TOTAL)
35 mA
TYPICAL SUPPLY
CURRENT
(TOTAL)
55 mA
TYPE
74F373
TYPE
74F374
TYPICAL f
max
165 MHz
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5 V
±
10%, T
amb
= 0
°C
to +70
°C
20-pin plastic DIP
20-pin plastic SOL
20-pin plastic SSOP type II
N74F373N, N74F374N
N74F373D, N74F374D
N74F373DB, N74F374DB
SOT146-1
SOT163-1
SOT339-1
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0 - D7
E (74F373)
OE
CP (74F374)
Q0 - Q7
Data inputs
Enable input (active-HIGH)
Output enable inputs (active-LOW)
Clock pulse input (active rising edge)
3-State outputs
DESCRIPTION
74F (U.L.)
HIGH / LOW
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
150 / 40
LOAD VALUE
HIGH/LOW
20
µA /
0.6 mA
20
µA /
0.6 mA
20
µA /
0.6 mA
20
µA /
0.6 mA
3.0 mA / 24 mA
NOTE:
One (1.0) FAST unit load is defined as: 20
µA
in the HIGH state and 0.6 mA in the LOW state.
2002 Nov 20
2
Philips Semiconductors
Product data
Latch/flip-flop
74F373/74F374
FUNCTION TABLE FOR 74F374
INPUTS
OE
L
L
L
H
CP
↑
↑
↑
↑
Dn
l
h
X
X
INTERNAL
REGISTER
L
H
NC
NC
OUTPUTS
Q0 – Q7
L
H
NC
Z
Hold
Disable outputs
OPERATING MODE
Load and read register
H
↑
Dn
Dn
Z
NOTES:
H =
High-voltage level
h =
HIGH state must be present one set-up time before the LOW-to-HIGH clock transition
L =
Low-voltage level
l =
LOW state must be present one set-up time before the LOW-to-HIGH clock transition
NC=
No change
X =
Don’t care
Z =
High impedance “off” state
↑
=
LOW-to-HIGH clock transition
Not LOW-to-HIGH clock transition
↑
=
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in HIGH output state
Current applied to output in LOW output state
Operating free air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
HIGH-level input voltage
LOW-level input voltage
Input clamp current
HIGH-level output current
LOW-level output current
Operating free air temperature range
PARAMETER
MIN
4.5
2.0
–
–
–
–
0
NOM
5.0
–
–
–
–
–
–
MAX
5.5
–
0.8
–18
–3
24
+70
UNIT
V
V
V
mA
mA
mA
°C
2002 Nov 20
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
