74VHC08; 74VHCT08
Quad 2-input AND gate
Rev. 01 — 30 June 2009
Product data sheet
1. General description
The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
2. Features
I
I
I
I
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accepts voltages higher than V
CC
Input levels:
N
The 74VHC08 operates with CMOS logic levels
N
The 74VHCT08 operates with TTL logic levels
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101C exceeds 1000 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74VHC08D
74VHCT08D
74VHC08PW
74VHCT08PW
74VHC08BQ
74VHCT08BQ
−40 °C
to +125
°C
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
Name
SO14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
4. Functional diagram
1
2
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
2Y
6
5
&
6
A
Y
&
8
B
mna221
&
3
3Y
8
9
10
4Y
11
12
&
mna222
11
13
mna223
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
74VHC08
74VHCT08
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
001aak040
74VHC08
74VHCT08
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
8
3A
3Y
terminal 1
index area
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
GND
3Y
8
GND
(1)
14 V
CC
13 4B
12 4A
11 4Y
10 3B
9
3A
1A
1
001aak041
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
74VHC_VHCT08_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 30 June 2009
2 of 14
NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
5.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function selection
[1]
Output
nB
X
L
H
nY
L
L
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
−0.5
V to (V
CC
+ 0.5 V)
[1]
[1]
Conditions
Min
−0.5
−0.5
−20
-
-
-
−75
−65
Max
+7.0
+7.0
-
±20
±25
75
-
+150
Unit
V
V
mA
mA
mA
mA
mA
°C
74VHC_VHCT08_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 30 June 2009
3 of 14
NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
Table 4.
Limiting values
…continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
P
tot
Parameter
total power dissipation
SO14 package
TSSOP14 package
DHVQFN14 package
[1]
[2]
[3]
[4]
Conditions
T
amb
=
−40 °C
to +125
°C
[2]
[3]
[4]
Min
-
-
-
Max
500
500
500
Unit
mW
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
P
tot
derates linearly with 8 mW/K above 70
°C.
P
tot
derates linearly with 5.5 mW/K above 60
°C.
P
tot
derates linearly with 4.5 mW/K above 60
°C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise
and fall rate
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Conditions
74VHC08
Min
2.0
0
0
−40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
100
20
74VHCT08
Min
4.5
0
0
−40
-
-
Typ
5.0
-
-
+25
-
-
Max
5.5
5.5
V
CC
+125
-
20
V
V
V
°C
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
For type 74VHC08
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
−50 µA;
V
CC
= 2.0 V
I
O
=
−50 µA;
V
CC
= 3.0 V
I
O
=
−50 µA;
V
CC
= 4.5 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
I
O
=
−8.0
mA; V
CC
= 4.5 V
74VHC_VHCT08_1
Conditions
Min
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.58
3.94
25
°C
Typ
-
-
-
-
-
-
2.0
3.0
4.5
-
-
Max
-
-
-
0.5
0.9
1.65
-
-
-
-
-
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.48
3.8
Max
-
-
-
0.5
0.9
1.65
-
-
-
-
-
Min
1.5
2.1
3.85
-
-
-
1.9
2.9
4.4
2.4
3.7
Max
-
-
-
0.5
0.9
1.65
-
-
-
-
-
V
V
V
V
V
V
V
V
V
V
V
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 30 June 2009
4 of 14
NXP Semiconductors
74VHC08; 74VHCT08
Quad 2-input AND gate
Table 6.
Static characteristics
…continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
OL
Conditions
Min
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 50
µA;
V
CC
= 2.0 V
I
O
= 50
µA;
V
CC
= 3.0 V
I
O
= 50
µA;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
O
= 8.0 mA; V
CC
= 4.5 V
I
I
I
CC
C
I
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
-
-
-
-
-
-
-
-
25
°C
Typ
0
0
0
-
-
-
-
3.0
Max
0.1
0.1
0.1
0.36
0.36
0.1
2.0
10
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
-
-
-
-
-
-
-
-
Max
0.1
0.1
0.1
0.44
0.44
1.0
20
10
Min
-
-
-
-
-
-
-
-
Max
0.1
0.1
0.1
0.55
0.55
2.0
40
10
V
V
V
V
V
µA
µA
pF
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
input
capacitance
HIGH-level
input voltage
LOW-level
input voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
For type 74VHCT08
V
IH
V
IL
V
OH
2.0
-
-
-
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
HIGH-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
=
−50 µA
I
O
=
−8.0
mA
LOW-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
= 50
µA
I
O
= 8.0 mA
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
4.4
3.94
-
-
-
-
-
4.5
-
0
-
-
-
-
-
-
0.1
0.36
0.1
2.0
1.35
4.4
3.8
-
-
-
-
-
-
-
0.1
0.44
1.0
20
1.5
4.4
3.7
-
-
-
-
-
-
-
0.1
0.55
2.0
40
1.5
V
V
V
V
µA
µA
mA
V
OL
I
I
I
CC
∆I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional
per input pin;
supply current V
I
= V
CC
−
2.1 V; I
O
= 0 A;
other pins at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
input
capacitance
C
I
-
3.0
10
-
10
-
10
pF
74VHC_VHCT08_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 30 June 2009
5 of 14
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