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IDT82V2081PP: 产品描述SINGLE CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT; 文件大小791KB，共68页; 制造商IDT(艾迪悌); 官网地址http://www.idt.com/

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IDT82V2081PP概述

SINGLE CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/

SHORT HAUL LINE INTERFACE UNIT

IDT82V2081

FEATURES:

•

Single channel T1/E1/J1 long haul/short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024

KHz

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703,G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR12/13

- AT&T Pub 62411

Software programmable or hardware selectable on:

- Wave-shaping templates for short haul and long haul LBO (Line Build

Out)

- Line terminating impedance (T1:100

Ω,

J1:110

Ω,

E1:75

Ω/120 Ω)

- Adjustment of arbitrary pulse shape

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

- B8ZS/HDB3/AMI line encoding/decoding

Active edge of transmit clock (TCLK) and receive clock (RCLK)

Active level of transmit data (TDATA) and receive data (RDATA)

Receiver or transmitter power down

High impedance setting for line drivers

PRBS (Pseudo Random Bit Sequence) generation and detection

with 2

-1 PRBS polynomials for E1

- QRSS (Quasi Random Sequence Signals) generation and detection

with 2

-1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Cable attenuation indication

Adaptive receive sensitivity

Short circuit protection and internal protection diode for line driv-

ers

LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection

Supports serial control interface, Motorola and Intel Multiplexed

interfaces and hardware control mode

Package:

IDT82V2081: 44-pin TQFP

•

DESCRIPTION:

The IDT82V2081 can be configured as a single channel T1, E1 or J1 Line

Interface Unit. In receive path, an Adaptive Equalizer is integrated to

remove the distortion introduced by the cable attenuation. The IDT82V2081

also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and

detects and reports the LOS conditions. In transmit path, there is an AMI/

B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter

Attenuator, which can be placed in either the receive path or the transmit

path. The Jitter Attenuator can also be disabled. The IDT82V2081 supports

both Single Rail and Dual Rail system interfaces. To facilitate the network

maintenance, a PRBS/QRSS generation/detection circuit is integrated in

the chip, and different types of loopbacks can be set according to the appli-

cations. Four different kinds of line terminating impedance, 75

Ω,

100

Ω,

110

Ω

and 120

Ω

are selectable. The chip also provides driver short-circuit

protection and internal protection diode. The chip can be controlled by either

software or hardware.

The IDT82V2081 can be used in LAN, WAN, Routers, Wireless Base

Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,

CSU/DSU equipment, etc.

INDUSTRIAL TEMPERATURE RANGES



The IDT logo is a registered trademark of Integrated Device Technology, Inc.

July 2004

DSC-6228/4

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

TABLE OF CONTENTS

IDT82V2081 PIN CONFIGURATIONS .......................................................................................... 8

PIN DESCRIPTION ....................................................................................................................... 9

FUNCTIONAL DESCRIPTION .................................................................................................... 15

3.1

CONTROL MODE SELECTION ....................................................................................... 15

3.2

T1/E1/J1 MODE SELECTION .......................................................................................... 15

3.3

TRANSMIT PATH ............................................................................................................. 15

3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 15

3.3.2 ENCODER ............................................................................................................. 15

3.3.3 PULSE SHAPER .................................................................................................... 15

3.3.3.1 Preset Pulse Templates .......................................................................... 15

3.3.3.2 LBO (Line Build Out) ............................................................................... 16

3.3.3.3 User-Programmable Arbitrary Waveform ................................................ 16

3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 20

3.3.5 TRANSMIT PATH POWER DOWN ........................................................................ 20

3.4

RECEIVE PATH ............................................................................................................... 21

3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 21

3.4.2 LINE MONITOR ...................................................................................................... 22

3.4.3 ADAPTIVE EQUALIZER......................................................................................... 22

3.4.4 RECEIVE SENSITIVITY ......................................................................................... 22

3.4.5 DATA SLICER ........................................................................................................ 22

3.4.6 CDR (Clock & Data Recovery)................................................................................ 22

3.4.7 DECODER .............................................................................................................. 22

3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 23

3.4.9 RECEIVE PATH POWER DOWN........................................................................... 23

3.5

JITTER ATTENUATOR .................................................................................................... 23

3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 23

3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 23

3.6

LOS AND AIS DETECTION ............................................................................................. 24

3.6.1 LOS DETECTION ................................................................................................... 24

3.6.2 AIS DETECTION .................................................................................................... 25

3.7

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 26

3.7.1 TRANSMIT ALL ONES ........................................................................................... 26

3.7.2 TRANSMIT ALL ZEROS......................................................................................... 26

3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 26

3.8

LOOPBACK ...................................................................................................................... 26

3.8.1 ANALOG LOOPBACK ............................................................................................ 26

3.8.2 DIGITAL LOOPBACK ............................................................................................. 26

3.8.3 REMOTE LOOPBACK............................................................................................ 26

3.8.4 INBAND LOOPBACK.............................................................................................. 28

3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 28

3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 28

3.8.4.3 Automatic Remote Loopback .................................................................. 28

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29

3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 29

3.9.2 ERROR DETECTION AND COUNTING ................................................................ 29

3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30

LINE DRIVER FAILURE MONITORING ........................................................................... 30

MCLK AND TCLK ............................................................................................................. 31

3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 31

3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 31

MICROCONTROLLER INTERFACES ............................................................................. 32

3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 32

3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 32

INTERRUPT HANDLING .................................................................................................. 33

5V TOLERANT I/O PINS .................................................................................................. 33

RESET OPERATION ........................................................................................................ 33

POWER SUPPLY ............................................................................................................. 33

PROGRAMMING INFORMATION .............................................................................................. 34

4.1

4.2

4.2.1 CONTROL REGISTERS......................................................................................... 35

4.2.2 TRANSMIT PATH CONTROL REGISTERS........................................................... 36

4.2.3 RECEIVE PATH CONTROL REGISTERS ............................................................. 38

4.2.4 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 40

4.2.5 INTERRUPT CONTROL REGISTERS ................................................................... 43

4.2.6 LINE STATUS REGISTERS ................................................................................... 46

4.2.7 INTERRUPT STATUS REGISTERS ...................................................................... 48

4.2.8 COUNTER REGISTERS ........................................................................................ 49

HARDWARE CONTROL PIN SUMMARY .................................................................................. 50

TEST SPECIFICATIONS ............................................................................................................ 52

MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 63

7.1

SERIAL INTERFACE TIMING .......................................................................................... 63

7.2

PARALLEL INTERFACE TIMING ..................................................................................... 64

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL

TEMPERATURE RANGES

LIST OF TABLES

Table-1

Table-2

Table-3

Table-4

Table-5

Table-6

Table-7

Table-8

Table-9

Table-10

Table-11

Table-12

Table-13

Table-14

Table-15

Table-16

Table-17

Table-18

Table-19

Table-20

Table-21

Table-22

Table-23

Table-24

Table-25

Table-26

Table-27

Table-28

Table-29

Table-30

Table-31

Table-32

Table-33

Table-34

Table-35

Table-36

Table-37

Table-38

Table-39

Table-40

Table-41

Table-42

Table-43

Table-44

Table-45

Table-46

Pin Description ................................................................................................................ 9

Transmit Waveform Value For E1 75

Ω

........................................................................ 17

Transmit Waveform Value For E1 120

Ω

...................................................................... 17

Transmit Waveform Value For T1 0~133 ft................................................................... 17

Transmit Waveform Value For T1 133~266 ft............................................................... 18

Transmit Waveform Value For T1 266~399 ft............................................................... 18

Transmit Waveform Value For T1 399~533 ft............................................................... 18

Transmit Waveform Value For T1 533~655 ft............................................................... 18

Transmit Waveform Value For J1 0~655 ft ................................................................... 19

Transmit Waveform Value For DS1 0 dB LBO.............................................................. 19

Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 19

Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 19

Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 20

Impedance Matching for Transmitter ............................................................................ 20

Impedance Matching for Receiver ................................................................................ 21

Criteria of Starting Speed Adjustment........................................................................... 23

LOS Declare and Clear Criteria for Short Haul Mode ................................................... 24

LOS Declare and Clear Criteria for Long Haul Mode.................................................... 25

AIS Condition ................................................................................................................ 25

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 26

EXZ Definition ............................................................................................................... 29

Interrupt Event............................................................................................................... 33

Register List and Map ................................................................................................... 34

ID: Device Revision Register ........................................................................................ 35

RST: Reset Register ..................................................................................................... 35

GCF: Global Configuration Register ............................................................................. 35

TERM: Transmit and Receive Termination Configuration Register .............................. 35

JACF: Jitter Attenuation Configuration Register ........................................................... 36

TCF0: Transmitter Configuration Register 0 ................................................................. 36

TCF1: Transmitter Configuration Register 1 ................................................................. 37

TCF2: Transmitter Configuration Register 2 ................................................................. 37

TCF3: Transmitter Configuration Register 3 ................................................................. 38

TCF4: Transmitter Configuration Register 4 ................................................................. 38

RCF0: Receiver Configuration Register 0..................................................................... 38

RCF1: Receiver Configuration Register 1..................................................................... 39

RCF2: Receiver Configuration Register 2..................................................................... 40

MAINT0: Maintenance Function Control Register 0...................................................... 40

MAINT1: Maintenance Function Control Register 1...................................................... 41

MAINT2: Maintenance Function Control Register 2...................................................... 41

MAINT3: Maintenance Function Control Register 3...................................................... 41

MAINT4: Maintenance Function Control Register 4...................................................... 42

MAINT5: Maintenance Function Control Register 5...................................................... 42

MAINT6: Maintenance Function Control Register 6...................................................... 42

INTM0: Interrupt Mask Register 0 ................................................................................. 43

INTM1: Interrupt Masked Register 1 ............................................................................. 44

INTES: Interrupt Trigger Edge Select Register ............................................................. 45

IDT82V2081PP

IDT82V2081PP概述

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