TB62747AFG/AFNG/AFNAG/BFNAG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62747AFG,TB62747AFNG,
TB62747AFNAG,TB62747BFNAG
16-Output Constant Current LED Driver
TB62747AFG
The TB62747 series is comprised of constant-current drivers
designed for LEDs and LED panel displays.
The regulated current sources are designed to provide a
constant current, which is adjustable through one external
resistor.
The TB62747 series incorporates 16 channels of shift registers,
latches, AND gates and constant-current outputs.
Fabricated using the Bi-CMOS process, the TB62747 series
satisfies the system requirement of high-speed data transmission.
The TB62747 series is RoHS compatible
SSOP24-P-300-1.00B
TB62747AFNG
SSOP24-P-300-0.65A
TB62747AFNAG/BFNAG
P-SSOP24-0409-0.64-001
Features
•
•
•
Power supply voltages: V
DD
=
3.3 V to 5.0 V
16-output built-in
Output current setting range
: 1.5 to 35 mA @ V
DD
=
3.3 V, V
O
= 0.4 to 1.0 V
Weight
SSOP24-P-300-1.00B : 0.29 g (typ.)
SSOP24-P-300-0.65A : 0.14 g (typ.)
P-SSOP24-0409-0.64-001: 0.14 g (typ.)
: 1.5 to 45 mA @ V
DD
=
5.0 V, V
O
= 0.4 to 1.2 V
•
•
Constant current output voltage: V
O
= 26 V (max)
Current accuracy (@ R
EXT
= 1.2 kΩ, V
O
= 0.4 V, V
DD
= 3.3 V, 5.0 V)
: Between outputs:
±
1.5 % (max)
: Between devices:
±
1.5 % (max)
Fast response of output current : t
wOE(L)
= 100 ns (min)
•
•
•
•
•
•
•
Control data format: serial-in, parallel-out
Input signal voltage level: 3.3 V and 5 V CMOS interfaces (Schmitt trigger input)
Serial data transfer rate: 25 MHz (max) @cascade connection
Operation temperature range: T
opr
= −40
to 85 °C
Power on reset (POR)
Package
: AFG type
: AFNG type
: AFNAG type
: BFNAG type
: SSOP24-P-300-1.00B
: SSOP24-P-300-0.65A
: P-SSOP24-0409-0.64-001
: P-SSOP24-0409-0.64-001
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Pin Assignment (top view)
TB62747AFG/AFNG/AFNAG
GND
SIN
SCK
SLAT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
TB62747BFNAG
OUT14
OUT15
OE
OUT13
V
DD
R
EXT
SOUT
OE
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT12
OUT11
OUT10
OUT9
OUT8
OUT7
SOUT
R
EXT
V
DD
GND
SIN
SCK
SLAT
OUT0
OUT1
OUT6
OUT5
OUT4
OUT3
OUT2
Note1: Short circuiting an output pin to a power supply pin (V
DD
or V
LED*
), or short-circuiting the R
EXT
pin to
the GND pin will likely exceed the rating, which in turn may result in smoldering and/or permanent
damage. Please keep this in mind when determining the wiring layout for the power supply and GND pins.
*V
LED
: LED power supply
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Block Diagram
OUT0
OUT1
OUT15
V
DD
OUT0
OUT1
Constant current outputs
OUT15
B.G
POR
GND
R
EXT
OE
SLAT
G
D0
Q0 Q1
Q15
16-bit D-latch
D0 D1
D15
Q0 Q1
Q15
16-bit shift register
R
SIN
SCK
Q15
R
SOUT
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Truth Table
SCK
SLAT
OE
SIN
Dn
Dn
+
1
Dn
+
2
Dn
+
3
Dn
+
3
OUT0
…
OUT7
…
OUT15
*1
SOUT
Dn
−
15
Dn
−
14
Dn
−
13
Dn
−
13
Dn
−
13
H
L
H
−*2
−*2
L
L
L
L
H
Dn … Dn
−
7 … Dn
−
15
No Change
Dn
+
2 … Dn
−
5 … Dn
−
13
Dn
+
2 … Dn
−
5 … Dn
−
13
OFF
Note1: When
OUT0
to
OUT15
output pins are set to "H" the respective output will be ON and when set to
"L" the respective output will be OFF.
Note2: “-“ is irrelevant to the truth table.
Timing Diagram
n
=
0
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
H
L
H
L
H
L
H
L
ON
OUT0
SIN
SLAT
OE
OFF
ON
OUT1
OFF
ON
OFF
OUT2
OUT15
ON
OFF
SOUT
H
L
Note 1:
Note 2:
The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit.
Keep the
SLAT
pin is set to “L” to enable the latch circuit to hold data. In addition, when the
SLAT
pin
is set to “H” the latch circuit does not hold data. The data will instead pass onto output.
When the
OE
pin is set to “L” the
OUT0
to
OUT15
output pins will go ON and OFF in response to
the data. In addition, when the
OE
pin is set to “H” all the output pins will be forced OFF regardless of
the data.
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2009-01-21
TB62747AFG/AFNG/AFNAG/BFNAG
Pin Functions
Pin No
AFG
AFNG
AFNAG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
GND
SIN
SCK
SLAT
OUT0
OUT1
OUT2
Pin Name
BFNAG
I/O
Function
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
O
The ground pin.
The serial data input pin.
The serial data transfer clock input pin.
The latch signal input pin.
Data is saved at L level.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
A sink type constant current output pin.
The constant current output enable signal input pin.
During the “H” level, the output will be forced off.
The serial data output pin.
The constant current value setting resistor connection pin.
The power supply input pin.
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
OE
SOUT
R
EXT
V
DD
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2009-01-21
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