Intel
®
82571 & 82572 Gigabit Ethernet
Controller
Datasheet
Revision 2.0
December 2006
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Copyright © Intel Corporation, 2003 - 2006
ii
Datasheet—82571/82572 Ethernet Controller
Revision History
Date
Oct 2002
Feb 2003
Revision
0.15
0.5
Initial Release
Revised ballout, added package drawing, added visual pin descriptions,
changed some ball names to “EXP” ball naming convention.
•
•
•
•
•
•
•
•
•
•
•
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Updated power specifications.
Changed names to “PE” naming convention
Revised signal descriptions, pinout information tables, and ballout grid.
Modified LAN disable ballout to cover A-0 (DEV_DIS_N) and B-0
(DEV_OFF_N).
Removed integrated Baseboard Management Controller.
Updated operating temperature
Changed DEV_DIS_N pin (A Stepping) to RSVD_NC
Corrected LED descriptions in signal descriptions in signal descriptions
Added Absolute Maximum Ratings
Added General Operating Conditions
Added Power Specifications
Added voltage Ramp and Sequencing Recommendations
Added DC I/O Specifications
Added Timing Specifications
Edited Thermal Characteristics
Section 4.4, Figure 2; Section 4.5.1.1;Section 4.5.1.2, Figure 5; Section
4.5.2, Figure 6; Section 5.1, Figure 7; Section 5.1, Figure 8; Section 5.4,
Figure 9, ball T6 changed to PERST_N.
Included 82572EI information
Updated signal names
Updated power numbers
Corrected 1.1 V Operating Range in Table 2
Changed document status to “Intel Confidential,” updated power values,
made minor corrections to text
Corrected pinlists
Pin A7 DEVICE_DIS_N has been moved to Reserved and No Connect
Signals; this pin is now Reserved. Refer to 82571EB/82571EI Design Guide
for guidance on proper connection.
Pin R4 LAN_PWR_GOOD has been moved to Reserved and No Connect
Signals; this pin is now Reserved. Refer to 82571EB/82571EI Design Guide
for guidance on proper connection.
Corrected signal names; minor text edits
Changed signal names PERST# to PE_RST_N and PE_WAKEn to
PE_WAKE_N; SMBCLK1 and SMBD1 are now reserved--Do not use these
pins--connect them to 3.3 V through a 100K ohms resistor; updated
schematics.
Notes
Aug 2003
0.6
Oct 2003
0.75
May 2004
0.85
January
2005
May 2005
Nov 2005
0.90
0.92
1.0
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March
2006
1.1
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August
2006
December
2006
1.2
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2.0
iii
82571/82572 Ethernet Controller—Datasheet
Contents
1.0
Introduction
.............................................................................................................
1.1
Document Scope ................................................................................................
1.2
Reference Documents..........................................................................................
1.3
Block Diagram....................................................................................................
1
1
1
3
2.0
Features of the 82571/82572 Gigabit Ethernet Controller.........................................
5
2.1
PCI Express Features .......................................................................................... 5
2.2
MAC-Specific Features ......................................................................................... 5
2.3
PHY Specific Features .......................................................................................... 6
2.4
Host Offloading Features...................................................................................... 6
2.5
Manageability Features ........................................................................................ 7
2.6
Additional Device Features ................................................................................... 7
2.7
Technology Features ........................................................................................... 8
Signal Descriptions
................................................................................................... 9
3.1
Signal Type Definitions ........................................................................................ 9
3.2
PCI Express Interface .......................................................................................... 9
3.3
Power Management Signals.................................................................................10
3.4
SMB and Fast Management Link Bus Signals..........................................................11
3.5
EEPROM and Serial FLASH Interface Signals ..........................................................12
3.6
LED Signals ......................................................................................................12
3.7
Other Signals ....................................................................................................13
3.8
Crystal Signals ..................................................................................................13
3.9
PHY Analog Signals ............................................................................................13
3.9.1 Port 0 ...................................................................................................13
3.9.2 Port 1 (82571 Only) ................................................................................14
3.10 Serializer / Deserializer Signals............................................................................15
3.11 Test Interface Signals.........................................................................................15
3.12 Power Supply Connections ..................................................................................16
3.12.1 Digital and Analog Supplies ......................................................................16
3.12.2 Grounds, Reserved Pins and No Connects...................................................16
Voltage, Temperature, and Timing Specifications.....................................................17
4.1
Targeted Absolute Maximum Ratings ....................................................................17
4.2
Targeted Recommended Operating Conditions .......................................................17
4.2.1 General Operating Conditions ...................................................................17
4.2.2 Voltage Ramps .......................................................................................18
4.2.3 Voltage Power Sequencing Options............................................................19
4.3
DC Specifications ...............................................................................................19
4.3.1 Power Specifications--82571EB.................................................................19
4.3.2 Power Specifications--82572EI .................................................................21
4.3.3 I/O Characteristics ..................................................................................22
4.4
Targeted AC Characteristics ................................................................................23
4.5
Targeted Timing Specifications ............................................................................24
4.5.1 PCI Express Interface ..............................................................................25
4.5.2 EEPROM Interface ...................................................................................28
4.5.3 FLASH Interface .....................................................................................29
Package and Pinout Information
..............................................................................31
5.1
Package Information ..........................................................................................31
5.2
Thermal Specification .........................................................................................33
5.3
Pinout Information .............................................................................................33
5.4
Visual Pin Assignments .......................................................................................44
3.0
4.0
5.0
iv
Datasheet—82571/82572 Gigabit Ethernet Controller
1.0
Introduction
The Intel
®
82571EB Gigabit Ethernet Controller is a single, compact component with
two full-integrated Gigabit Ethernet Media Access Control (MAC) and physical layer
(PHY) ports. The Intel 82571/82572 Gigabit Ethernet Controller is a single-port version
of the controller in the same package. These devices use the PCI Express* architecture
(Rev. 1.0a). The Intel 82571/82572 Gigabit Ethernet Controller enables dual- or single-
port gigabit ethernet implementation in a very small area--ideal for both server and
workstation network designs that have critical space constraints.
The Intel 82571/82572 Gigabit Ethernet Controller provides a standard IEEE 802.3
Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3,
802.3u, and 802.3ab). Ports also contain a Serializer-Deserializer (SERDES) to support
1000Base-SX/LX (optical fiber) and Gigabit backplane applications. In addition to
managing MAC and PHY Ethernet layer functions, the controller manages PCI Express
packet traffic across its transaction, link, and physical/logical layers.
The Intel 82572EI Gigabit Ethernet Controller’s on-board System Management Bus
(SMB) ports enable network manageability implementations required by information
technology personnel for remote control and alerting via the LAN. With SMB,
management packets can be routed to or from a management processor. The SMB
ports enable industry standards, such as Alert Standard Format (ASF) 2.0, to be
implemented using the 82571/82572 Gigabit Ethernet Controller. In addition, on-chip
ASF 2.0 circuitry provides alerting and remote control capabilities with standardized
interfaces. Enhanced pass-through capabilities also allow system remote control over
standardized interfaces.
The 82571/82572 Gigabit Ethernet Controller with PCIe* architecture is designed for
high performance and low memory latency. The device is optimized to connect to a
system Memory Control Hub (MCH) using four PCI Express lanes. Alternatively, the
82571/82572 Gigabit Ethernet Controller controller can connect to an I/O Control Hub
(ICH6 & 7) that has a PCI Express interface.
Wide internal data paths eliminate performance bottlenecks by efficiently handling
large address and data words. Combining a parallel and pipe-lined logic architecture
optimized for gigabit ethernet and independent transmit and receive queues, the
82571/82572 Gigabit Ethernet Controller efficiently handles packets with minimum
latency. The 82571/82572 Gigabit Ethernet Controller includes advanced interrupt
handling features. The 82571/82572 Gigabit Ethernet Controller uses efficient ring
buffer descriptor data structures, with up to 64 packet descriptors cached on-chip. A
large 48 KByte per port on-chip packet buffer maintains superior performance. In
addition, using hardware acceleration, the controller offloads tasks from the host, such
as TCP/UDP/IP checksum calculations and TCP segmentation.
The 82571/82572 Gigabit Ethernet Controller is packaged in a 17 mm x 17 mm, 256-
ball grid array.
1.1
Document Scope
This document contains targeted datasheet specifications for the 82571/82572 Gigabit
Ethernet Controller, including signal descriptions, DC and AC parameters, packaging
data, and pinout information.
1.2
Reference Documents
This application assumes that the designer is acquainted with high-speed design and
board layout techniques. The following documents provide additional information:
• 82571/82572 Gigabit Ethernet Controller Design Guide. Intel Corporation.
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