S i 5 2 1 3 1 - A 11 A
P CI-E
XP RE SS
G
EN
1 , G
E N
2, & G
EN
3 T
W O
O
U T P U T
C
LOCK
G
E N E R
-
A T O R W I T H
25 MH
Z
R
E F E RE NCE
C
LOCK
& A
C T I V E
L
OW
OE P
IN S
Features
PCI-Express Gen1, Gen2 &
Gen3 Compliant
Supports Serial ATA (SATA) at
100 MHz
Low power differential output
buffers
No termination resistors required
Dedicated active low output
enable pins for each output
Pin selectable spread control
Selectable frequencies: 100, 125,
and 200 MHz
Up two PCI-Express clocks
25 MHz reference clock
25 MHz Crystal Input or Clock
input
I
2
C support with readback
capabilities
Triangular spread spectrum
profile for maximum
electromagnetic interference
(EMI) reduction
Extended Temperature
–40 to 85
o
C
3.3 V Power supply
24-pin QFN package
Ordering Information:
See page 17
Pin Assignments
VSS_CORE
XIN/CLKIN
VDD_CORE
SDATA
SCLK
Network Attached Storage
Wireless Access Point
Multi-function Printer
Routers
Ideal for Thunderbolt applications
24
VDD_REF
REF
OE_REF
1
1
2
3
4
5
6
7
1
23
22
XOUT
Applications
21
20
19
1
18 OE_DIFF1
17 VDD_DIFF
16 DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
8
SS1
1
Description
Si52131-A11A is a high-performance, PCIe clock generator that can
source two PCIe clocks and a buffered 25 MHz reference clock from a
25 MHz crystal or clock input. The PCIe clock outputs are compliant to
PCIe Gen 1, Gen 2, and Gen 3 specifications. The device has three
active low output enable pins for enabling and disabling each output. The
device features two input select pins for frequency selection and spread
control. The small footprint and low power consumption makes Si52131-
A11A the ideal clock solution for consumer and embedded applications.
VSS_REF
OE_DIFF0
1
VDD_DIFF
25
GND
9
NC
10
NC
11
NC
12
VDD_DIFF
Note
1. Internal 100 k-ohm pull-down resistor
Patents pending
Functional Block Diagram
XIN/CLKIN
XOUT
25MHz
DIFF0
PLL1
(SSC)
Divider
DIFF1
SCLK
SDATA
OE#_REF
OE#_DIFF [1:0]
SSC [1:0]
Control
RAM
Control & Memory
Rev 1.0 3/13
Copyright © 2013 by Silicon Laboratories
SS0
Si52131-A11A
Si52131-A11A
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1. Crystal Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2. OE Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3. OE Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.4. OE Deassertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.5. SS[1:0] Pins Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2. Data Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5. Si52131-A11A Pin Descriptions 24-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Rev 1.0
3
Si52131-A11A
1. Electrical Specifications
Table 1. DC Electrical Specifications
Parameter
3.3 V Operating Voltage
3.3 V Input High Voltage
3.3 V Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Leakage Current
Input Low Leakage Current
3.3 V Output High Voltage
(SE)
3.3 V Output Low Voltage
(SE)
High-impedance Output
Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Power Down Current
Dynamic Supply Current
Symbol
VDD core
V
IH
V
IL
V
IHI2C
V
ILI2C
I
IH
I
IL
V
OH
V
OL
I
OZ
C
IN
C
OUT
L
IN
I
DD
_
PD
I
DD_3.3V
All outputs enabled. Differ-
ential clocks with 5” traces
and 2 pF load. 25 MHz clock
with 5” traces and 4 pF load
Test Condition
3.3 ±5%
SS1:0
SS1:0
SDATA, SCLK
SDATA, SCLK
Except internal pull-down
resistors, 0 < V
IN
< V
DD
Except internal pull-up resis-
tors, 0 < V
IN
< V
DD
I
OH
= –1 mA
I
OL
= 1 mA
Min
3.135
2.0
V
SS
– 0.3
2.2
—
—
–5
2.4
—
–10
1.5
—
—
—
—
Typ
3.3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
3.465
V
DD
+ 0.3
0.8
—
1.0
5
—
—
0.4
10
5
6
7
1
45
Unit
V
V
V
V
V
A
A
V
V
A
pF
pF
nH
mA
mA
4
Rev 1.0
Si52131-A11A
Table 2. AC Electrical Specifications
Parameter
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise/Fall Slew Rate
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
Duty Cycle
Cycle to Cycle Jitter
PCIe Gen 1 Pk-Pk Jitter
PCIe Gen 2 Phase Jitter
PCIe Gen 3 Phase Jitter
Long Term Accuracy
Rise/Fall Slew Rate
Voltage High
Voltage Low
Crossing Point Voltage at 0.7 V
Swing
Spread Range
Modulation Frequency
REF at 3.3 V
Duty Cycle
Rise/Fall Slew Rate
Cycle to Cycle Jitter
Long Term Accuracy
Enable/Disable and Setup
Symbol
L
ACC
T
DC
T
R
/T
F
T
CCJ
T
LTJ
V
IH
V
IL
I
IH
I
IL
T
DC
T
CCJ
Pk-Pk
RMS
GEN2
RMS
GEN3
L
ACC
T
R
/T
F
V
HIGH
V
LOW
V
OX
SPR-2
F
MOD
T
DC
T
R
/ T
F
T
CCJ
L
ACC
T
STABLE
T
SS
Test Condition
Measured at V
DD
/2 differential
Measured at V
DD
/2
Measured between 0.2 V
DD
and
0.8 V
DD
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
PCIe Gen 1
10 kHz < F < 1.5 MHz
1.5 MHz < F < Nyquist
Includes PLL BW 2–4 MHz,
CDR = 10 MHz
Measured at 0 V differential
Measured differentially from
±150 mV
Min
—
47
0.5
—
—
2
—
—
–35
45
—
0
0
0
0
—
1
—
–0.3
300
Typ
—
—
—
—
—
—
—
—
—
—
35
40
2
2
0.5
—
—
—
—
—
–0.5
31.5
—
—
—
—
—
—
Max
250
53
4.0
250
350
VDD+0.3
0.8
35
—
55
50
86
3.0
3.1
1.0
100
8
1.15
—
550
—
33
55
4.0
300
100
1.8
—
Unit
ppm
%
V/ns
ps
ps
V
V
µA
µA
%
ps
ps
ps
ps
ps
ppm
V/ns
V
V
mV
%
kHz
%
V/ns
ps
ppm
ms
ns
Down spread
—
30
Measurement at 1.5 V
Measured between 0.8 and 2.0 V
Measurement at 1.5 V
Measured at 1.5 V
45
1.0
—
—
—
10.0
Clock Stabilization from Power-up
Stopclock Setup Time
Note:
Visit
www.pcisig.com
for complete PCIe specifications.
Rev 1.0
5
嵌入式系统
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