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GS8182T37BGD-400IT: 产品描述DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165; 产品类别存储存储; 文件大小337KB，共27页; 制造商GSI Technology; 官网地址http://www.gsitechnology.com/; 标准

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GS8182T37BGD-400IT概述

DDR SRAM, 512KX36, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165

GS8182T37BGD-400IT规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	GSI Technology
零件包装代码	BGA
包装说明	LBGA, BGA165,11X15,40
针数	165
Reach Compliance Code	compliant
ECCN代码	3A991.B.2.B
最长访问时间	0.45 ns
其他特性	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)	400 MHz
I/O 类型	COMMON
JESD-30 代码	R-PBGA-B165
JESD-609代码	e1
长度	15 mm
内存密度	18874368 bit
内存集成电路类型	DDR SRAM
内存宽度	36
湿度敏感等级	3
功能数量	1
端子数量	165
字数	524288 words
字数代码	512000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	512KX36
输出特性	3-STATE
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装等效代码	BGA165,11X15,40
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE
并行/串行	PARALLEL
峰值回流温度（摄氏度）	260
电源	1.5/1.8,1.8 V
认证状态	Not Qualified
座面最大高度	1.4 mm
最大待机电流	0.185 A
最小待机电流	1.7 V
最大压摆率	0.575 mA
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	13 mm
Base Number Matches	1

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GS8182T19/37BD-435/400/375/333/300

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• 2.0 Clock Latency

• Simultaneous Read and Write SigmaDDR-II™ Interface

• Common I/O bus

• JEDEC-standard pinout and package

• Double Data Rate interface

• Byte Write (x36 and x18) function

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation with self-timed Late Write

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

18Mb SigmaDDR-II+

Burst of 2 SRAM

435 MHz–300 MHz

1.8 V V

1.8 V and 1.5 V I/O

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8182T19/37BD SigmaDDR-II+ SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer.

Each internal read and write operation in a SigmaDDR-II+ B2

RAM is two times wider than the device I/O bus. An input data

bus de-multiplexer is used to accumulate incoming data before

it is simultaneously written to the memory array. An output

data multiplexer is used to capture the data produced from a

single memory array read and then route it to the appropriate

output drivers as needed. Therefore the address field of a

SigmaDDR-II+ B2 RAM is always one address pin less than

the advertised index depth (e.g., the 2M x 8 has a 1M

addressable index).

SigmaDDR-II™ Family Overview

The GS8182T19/37BD are built in compliance with the

SigmaDDR-II+ SRAM pinout standard for Common I/O

synchronous SRAMs. They are 18,874,368-bit (18Mb)

SRAMs. The GS8182T19/37BD SigmaDDR-II SRAMs are

Parameter Synopsis

-435

tKHKH

tKHQV

2.3 ns

0.45 ns

-400

2.5 ns

0.45 ns

-375

2.67 ns

0.45 ns

-333

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

Rev: 1.03a 11/2011

1/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182T19/37BD-435/400/375/333/300

Background

Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.

Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are

unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed

Common I/O SRAM data bandwidth in half.

Burst Operations

Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will

respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in

the timing diagrams. This means that it is possible to load new addresses every K clock cycle. Addresses can be loaded less often,

if intervening deselect cycles are inserted.

Deselect Cycles

Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to

the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer

and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from

loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer

operations.

SigmaDDR-II+ B2 SRAM Read Cycles

The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read

command (LD low and R/W high) is clocked into the SRAM by a rising edge of K.

SigmaDDR-II+ B2 SRAM Write Cycles

The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.

Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command

(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures

data in on the next rising edge of K, for a total of two transfers per address load.

Rev: 1.03a 11/2011

5/27

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS8182T37BGD-400IT

GS8182T37BGD-400IT概述

GS8182T37BGD-400IT规格参数

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