74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
June 2014
74LVX3245
8-Bit, Dual-Supply Translating Transceiver with
3-State Outputs
Features
Bidirectional Interface Between 3 V and 5 V Buses
Inputs Compatible with TTL Level
3 V Data Flow at A-Port and 5 V Data Flow at B-
Port
Outputs Source / Sink: 24 mA
Guaranteed Simultaneous Switching Noise Level
and Dynamic Threshold Performance
Implements Proprietary EMI Reduction Circuitry
Functionally Compatible with the 74 Series 245
Description
The 74LVX3245 is a dual-supply, 8-bit translating
transceiver designed to interface between a 3 V bus and
a 5 V bus in a mixed 5 V supply environment. The
Transmit/ Receive (T/¯ ) input determines the direction
R
of data flow. Transmit (active-HIGH) enables data from
A-ports to B-ports; receive (active-LOW) enables data
from B-ports to A-ports. The output enable input, when
HIGH, disables both A- and B-ports by placing them in a
high-impedance condition. The A-port interfaces with
the 3 V bus; the B-port interfaces with the 5 V bus.
The 74LVX3245 is suitable for mixed-voltage
applications, such as notebook computers using 3.3 V
CPU and 5V peripheral components.
Related Resources
AN-5001 — Using Fairchild’s LVX Low-Voltage
Dual-Supply CMOS Translating Transceivers
Ordering Information
Part Number
74LVX3245WM
74LVX3245WMX
74LVX3245QSC
74LVX3245QSCX
74LVX3245MTC
74LVX3245MTCX
-40 to +85°C
Operating
Temperature Range
Package
24-Lead Small-Outline Integrated Circuit
(SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Quarter-Size Outline Package
(QSOP), JEDEC MO-137, 0.150" Wide
24-Lead Thin-Shrink Small-Outline
Package (TSSOP), JEDEC MO-153,
4.4 mm Wide
Packing Method
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.0.3
www.fairchildsemi.com
74LVX3245 — 8-Bit Dual-Supply Translating Transceiver with 3-State Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CCA
, V
CCB
Supply Voltage
V
IN
DC Input Voltage; (/OE, T/¯ )
R
Parameter
Min.
-0.5
-0.5
A
n
-0.5
-0.5
Max.
7.0
V
CCA
+0.5
V
CCA
to
+0.5
V
CCB
to
+0.5
±20
±50
±50
±50
Unit
V
V
V
I/O
DC Input / Output Voltage
B
n
V
I
IN
I
OK
I
O
DC Input Diode Current (/OE and T/¯ )
R
DC Output Diode Current
DC Output Source or Sink Current
Output Pin
I
CCA
I
CCB
-65
mA
mA
mA
mA
°C
mA
°C
V
I
CC
or I
GND
DC V
CC
or Ground Current
T
STG
I
SINK
T
J
ESD
Storage Temperature Range
Maximum Current at
±100
±200
+150
±300
+150
2500
DC Latch-Up Source or Sink Current
Maximum Junction Temperature Under Bias
Electrostatic Discharge
Capability
Human Body Model, JESD22-A114
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
V
CCA
V
CCB
V
I
V
I/O
T
A
∆t
/
∆V
Supply Voltage
Input Voltage (/OE and T/¯ )
R
DC Input / Output Voltage
Parameter
Min.
2.7
4.5
0
A
n
B
n
0
0
-40
Max.
3.6
5.5
V
CCA
V
CCA
V
CCB
+85
8
Unit
V
V
V
°C
ns/V
Operating Temperature, Free Air
Minimum Input Edge Rate (V
IN
from 30 to 70% of V
CC
, V
CC
at 3.0 V,
4.5 V, and 5.5 V)
Note:
1. Unused pins (inputs and I/O’s) must be held HIGH or LOW. They may not float.
© 1993 Fairchild Semiconductor Corporation
74LVX3245 • Rev. 1.0.3
www.fairchildsemi.com
4
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