KINETIS_2N03G
Rev. 26 AUG 2013
Mask Set Errata for Mask 2N03G
This document contains errata information for Kinetis Mask Set
2N03G but excludes any information on selected security-related
modules.
A nondisclosure agreement (NDA) is required for any security-related
module information.
For more information on obtaining an NDA, please contact your local
Freescale sales representative.
© 2013 Freescale Semiconductor, Inc.
Freescale Semiconductor
Mask Set Errata
KINETIS_2N03G
Rev 26 AUG 2013
Mask Set Errata for Mask 2N03G
Introduction
This report applies to mask 2N03G for these products:
• KINETIS
Errata ID
6804
6939
6940
5706
4710
6573
7214
6665
5130
3981
3982
4624
3977
4627
3980
3983
3978
3984
4218
4935
Errata Title
CJTAG: Performing a mode change from Standard Protocol to Advanced Protocol may reset the CJTAG.
Core: Interrupted loads to SP can cause erroneous behavior
Core: VDIV or VSQRT instructions might not complete correctly when very short ISRs are used
FTFx: MCU security is inadvertently enabled (secured) if a mass erase is executed when the flash blocks/
halves are swapped. This issue only affects applications that use the flash swap feature.
FTM: FTMx_PWMLOAD register does not support 8-/16-bit accesses
JTAG: JTAG TDO function on the PTA2 disables the pull resistor
Low Leakage Stop (LLS) mode non-functional
Operating requirements: Limitation of the device operating range
SAI: Under certain conditions, the CPU cannot reenter STOP mode via an asynchronous interrupt
wakeup event
SDHC: ADMA fails when data length in the last descriptor is less or equal to 4 bytes
SDHC: ADMA transfer error when the block size is not a multiple of four
SDHC: AutoCMD12 and R1b polling problem
SDHC: Does not support Infinite Block Transfer Mode
SDHC: Erroneous CMD CRC error and CMD Index error may occur on sending new CMD during data
transfer
SDHC: Glitch is generated on card clock with software reset or clock divider change
SDHC: Problem when ADMA2 last descriptor is LINK or NOP
SDHC: Software can not clear DMA interrupt status bit after read operation
SDHC: eSDHC misses SDIO interrupt when CINT is disabled
SIM/FLEXBUS: SIM_SCGC7[FLEXBUS] bit should be cleared when the FlexBus is not being used.
UART: CEA709.1 features not supported
Table continues on the next page...
© 2013 Freescale Semiconductor, Inc.
Errata ID
7027
7028
6472
4647
7029
7090
7031
5704
7091
7092
5928
6933
Errata Title
UART: During ISO-7816 T=0 initial character detection invalid initial characters are stored in the RxFIFO
UART: During ISO-7816 initial character detection the parity, framing, and noise error flags can set
UART: ETU compensation needed for ISO-7816 wait time (WT) and block wait time (BWT)
UART: Flow control timing issue can result in loss of characters if FIFO is not enabled
UART: In ISO-7816 T=1 mode, CWT interrupts assert at both character and block boundaries
UART: In ISO-7816 mode, timer interrupts flags do not clear
UART: In single wire receive mode UART will attempt to transmit if data is written to UART_D
UART: TC bit in UARTx_S1 register is set before the last character is sent out in ISO7816 T=0 mode
UART: UART_S1[NF] and UART_S1[PE] can set erroneously while UART_S1[FE] is set
UART: UART_S1[TC] is not cleared by queuing a preamble or break character
USBOTG: USBx_USBTRC0[USBRESET] bit does not operate as expected in all cases
eDMA: Possible misbehavior of a preempted channel when using continuous link mode
e6804: CJTAG: Performing a mode change from Standard Protocol to Advanced
Protocol may reset the CJTAG.
Errata type:
Errata
Description:
In extremely rare conditions, when performing a mode change from Standard Protocol to
Advanced Protocol on trhe IEEE 1149.7 (Compact JTAG interface) , the CJTAG may reset
itself. In this case, all internal CJTAG registers will be reset and the CJTAG will return to the
Standard Protocol mode.
Workaround:
If the CJTAG resets itself while attempting to change modes from Standard Protocol to
Advanced Protocol and Advanced Protocol cannot be enabled after several attempts, perform
future accesses in Standard Protocol mode and do not use the Advanced Protocol feature.
e6939: Core: Interrupted loads to SP can cause erroneous behavior
Errata type:
Errata
Description:
ARM Errata 752770: Interrupted loads to SP can cause erroneous behavior
Affects: Cortex-M4, Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
Description
If an interrupt occurs during the data-phase of a single word load to the stack-pointer (SP/
R13), erroneous behavior can occur. In all cases, returning from the interrupt will result in the
load instruction being executed an additional time. For all instructions performing an update to
the base register, the base register will be erroneously updated on each execution, resulting in
the stack-pointer being loaded from an incorrect memory location.
The affected instructions that can result in the load transaction being repeated are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
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Freescale Semiconductor, Inc.
3) LDR SP,[Rn,#imm]
4) LDR SP,[Rn]
5) LDR SP,[Rn,Rm]
The affected instructions that can result in the stack-pointer being loaded from an incorrect
memory address are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
Conditions
1) An LDR is executed, with SP/R13 as the destination
2) The address for the LDR is successfully issued to the memory system
3) An interrupt is taken before the data has been returned and written to the stack-pointer.
Implications
Unless the load is being performed to Device or Strongly-Ordered memory, there should be no
implications from the repetition of the load. In the unlikely event that the load is being
performed to Device or Strongly-Ordered memory, the repeated read can result in the final
stack-pointer value being different than had only a single load been performed.
Interruption of the two write-back forms of the instruction can result in both the base register
value and final stack-pointer value being incorrect. This can result in apparent stack corruption
and subsequent unintended modification of memory.
Workaround:
Both issues may be worked around by replacing the direct load to the stack-pointer, with an
intermediate load to a general-purpose register followed by a move to the stack-pointer.
If repeated reads are acceptable, then the base-update issue may be worked around by
performing the stack pointer load without the base increment followed by a subsequent ADD or
SUB instruction to perform the appropriate update to the base register.
e6940: Core: VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used
Errata type:
Errata
Description:
ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used
Affects: Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
On Cortex-M4 with FPU, the VDIV and VSQRT instructions take 14 cycles to execute. When
an interrupt is taken a VDIV or VSQRT instruction is not terminated, and completes its
execution while the interrupt stacking occurs. If lazy context save of floating point state is
enabled then the automatic stacking of the floating point context does not occur until a floating
point instruction is executed inside the interrupt service routine.
Lazy context save is enabled by default. When it is enabled, the minimum time for the first
instruction in the interrupt service routine to start executing is 12 cycles. In certain timing
conditions, and if there is only one or two instructions inside the interrupt service routine, then
the VDIV or VSQRT instruction might not write its result to the register bank or to the FPSCR.
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
Freescale Semiconductor, Inc.
3
Workaround:
A workaround is only required if the floating point unit is present and enabled. A workaround is
not required if the memory system inserts one or more wait states to every stack transaction.
There are two workarounds:
1) Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the
FPCCR at address 0xE000EF34).
2) Ensure that every interrupt service routine contains more than 2 instructions in addition to
the exception return instruction.
e5706: FTFx: MCU security is inadvertently enabled (secured) if a mass erase is
executed when the flash blocks/halves are swapped. This issue only affects
applications that use the flash swap feature.
Errata type:
Errata
Description:
When the logical addresses of the flash blocks (halves) are swapped via the flash swap control
command sequence and a mass erase is executed (via the MDM-AP or EzPort), the MCU
security can go from un-secure to secure. Thus, when using a debugger to erase the entire
flash memory and re-download a software application, the debugger may report that the device
is secure after the erase completes. This issue only affects applications that use the flash
swap feature.
Workaround:
Issue the mass erase request (via the MDM-AP or EzPort) a second time to un-secure the
device.
e4710: FTM: FTMx_PWMLOAD register does not support 8-/16-bit accesses
Errata type:
Errata
Description:
The FTM PWM Load register should support 8-bit and 16-bit accesses. However, the
FTMx_PWMLOAD[LDOK] bit is cleared automatically by FTM with these sized accesses, thus
disabling the loading of the FTMx_MOD, FTMx_CNTIN, and FTMx_CnV registers.
Workaround:
Always use a 32-bit write access to modify contents of the FTMx_PWMLOAD register.
e6573: JTAG: JTAG TDO function on the PTA2 disables the pull resistor
Errata type:
Errata
Description:
The JTAG TDO function on the PTA2 pin disables the pull resistor, but keeps the input buffer
enabled. Because the JTAG will tri-state this pin during JTAG reset (or other conditions), this
pin will float with the input buffer enabled. If the pin is unconnected in the circuit, there can be
increased power consumption in low power modes for some devices.
Workaround:
Disable JTAG TDO functionality when the JTAG interface is not needed and left floating in a
circuit. Modify the PORTA_PCR2 mux before entering low power modes. Set the mux to a pin
function other than ALT7. If set up as a digital input and left unconnected in the circuit, then a
pull-up or pull-down should be enabled. Alternatively, an external pull device or external source
can be added to the pin.
Note: Enabling the pull resistor on the JTAG TDO function violates the JTAG specification.
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
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